Cart New Account Login

HomeAbout usProductsSupportForumsBlogCustomer Service

Please accept the use of cookies on our site

At PEmicro we use web browser cookies in order to provide you with an enhanced experience and in order to be able to do things like shopping cart processing and identify you when you login to our website.

Click here to accept

search inside this forum
search inside all forums
KDS and MultiLink Universal Breakpoint Question
. Oct 29, 2015 at 03:46 PM (15:46 hours)
Staff: Gerardo R.

  • I am using KDS 3.0.0 with a Kinetis K10 micro controller under Windows, and seeing some "odd" behavior on a logic analyzer on my device data bus when debugging code using the MultiLink Universal.

    Basically, I can have 2 lines of code, that write to two external device addresses, and then hit a break point in my C code. So the logic analyzer should capture TWO writes to the registers on an external device, and I do indeed see those. However, almost invariably, I will capture an ADDITIONAL write or writes to the external device with my logic analyzer. Often these are writes that are PAST the break point in the debugger. And often the data or address value is not one that is ever used in my code - the processor is just generating an extra write cycle. I've also seen such behavior in the middle of a loop that writes 32KB of data to the device to program it, and in the middle of that loop, writing to TWO addresses, I sometimes see a 3rd address generated on the bus in between them. I.e. write to device address 0xA, 0xC and repeat 32000 times. 1400 cycles through a for loop in my C code the logic analyzer captures a write to 0xA, 0xB then 0xC. In the middle of a constant loop of 2 lines of code, writing to hard coded addresses 0xA and 0xC!

    Should the Multilink Universal not have the processor totally halted when it hits a breakpoint in KDS? I am trying to understand two issues I am seeing, and decide if they are artifacts of the fact that I am debugging, or something introduced by the Multilink. I hate to be chasing ghosts....


    Jim Morris


  • Just to confirm, you are observing this traffic directly from the debug lines? I'm not entirely sure how your logic analyzer parses all this. Debugging with the SWD protocol and ARM debug port requires a lot of traffic that isn't necessarily data read/writes to the processor's memory map. Interactive debug sessions like in KDS generates all sorts of unexpected traffic for instance in the breakpoint case, KDS has to update all the register views and disassembly. Also, to program the flash of the chip we do write a programming routine into RAM which simply reads from a buffer and programs the flash memory.

    Are you seeing these memory addresses changing data erroneously in the memory viewer?

Add comment

   Want to comment? Please login or create a new PEMicro account.

© 2018 P&E Microcomputer Systems Inc.
Website Terms of Use and Sales Agreement