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BDM and CSBOOT state
Tom M. May 7, 2021 at 09:51 AM (09:51 hours)
Staff: Johnny N.

  • I am not a programmer but rather a technician trying to improve testing of some boards that use the 68HC16Z1 chip. I came across an issue where the DATA0 line was not always properly pulled high during reset so the system booted in 8 bit mode not 16 bit. When using the ICD16Z software, it was very confusing to understand what was happening when this intermittent fault occurred.

    My question is, can one somehow see the state of DATA0 during reset, or whether CSBOOT is configured as 8 bit or 16 bit after reset, in some register somewhere?




    Comments

    • Hi Tom,

      https://www.nxp.com/docs/en/data-sheet/MC68HC16ZUM.pdf

      According to the 68HC16Z1 datasheet in Section 5.9.4 Chip-Select Reset Operation

      ---------------------------------------------------------------------------------

      The LSB of the CSBOOT field, determined by the logic level of DATA0 during reset,
      selects the boot ROM port size. When DATA0 is held low during reset, port size
      is eight bits. When DATA0 is held high during reset, port size is 16 bits. DATA0
      has a weak internal pull-up driver, so that a 16-bit port is selected by default

      However, the internal pull-up driver can be overcome by bus loading effects.
      To ensure a particular configuration out of reset, use an active device to put
      DATA0 in a known state during reset.

      ---------------------------------------------------------------------------------

      Maybe you can try reading back the DATA0 bit which is the LSB in the CSBOOT field of the CSPAR0 register? You can check $FFA44, which is the address we write to setup CSPAR0 in our HC16 algorithms. It might also be at address $FFFA44. You can use the mm command to read a memory mapped address or you can view it in the memory window. Check with other engineers on the NXP community forums to see if this is the only way to check the state of DATA0 out of reset.

      -Johnny

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