Programming Paged Memories for HC(S)12(X) Microcontrollers
On HC(S)12(X) with banked memories, the CPU uses logical addresses that do not directly correspond to physical flash addresses. Your toolchain will typically generate a record that corresponds to the logical memory map. Programming tools, however, operate on physical memory. This article goes into the process of converting your logical file to a physical file that is compatible with the PROG-HL-12Z or Cyclone software. When an S-Record containing the wrong type of addresses is provided, you will get the warning "All S record addresses not in range or module. Continue?". This must be resolved using our Log2Phy utility. Do I need Log2Phy? Log2Phy is required if: Log2Phy is NOT required if: The HC(S)12(X) microcontroller family uses a paged flash architecture to expand its addressable memory beyond the standard 64KB (or $0000 to $FFFF). Microcontrollers with this feature treat a 16KB block of memory from $8000 to $BFFF as a memory window. This window allows multiple 16KB blocks to be switched into and out of program memory. An 8-bit program page register (PPAGE) tells the microcontroller which block to read. Paging allows a small CPU-visible window to map to different regions of a larger physical memory space. Paged Flash The entire paged memory can be addressed in two different ways: logical or physical. Logical addresses are treated as segments of 16KB separated by 48KB. These segments (or pages) of memory occupy 0x8000 to 0xBFFF. In addition to the page window, there are two fixed 16KB blocks from 0x4000 to 0x7FFF and 0xC000 to 0xFFFF. These fixed locations are addressable in either range. For example, the physical address of the last page (0xFF) of the MC9S12XDP512 is 0x7FC000 to 0x7FFFFF. This maps to the logical address 0xFF8000 to 0xFFBFFF or the fixed window 0xC000 to 0xFFFF. Logical 0xFF8000 converts to -> Physical 0x7FC000 Physical addresses treat the whole flash as one linear space in a 24-bit memory map. For example, the physical address space of the entire flash on the MC9S12XDP512 is 0x780000-0x7FFFFF. Note for Codewarrior IDE users: Look in your project for a *.glo file. This file contains the data with physical addresses already compatible with our software. Steps to use Log2Phy: 1. Install and open Log2Phy 2. Select correct device from the DeviceType drop down box (critical) 3. Load the logical record file 4. Provide output path of physical S-record file. Default will be your file renamed with .phy extension 5. Press convert 6. Use .phy in programming tool The results of the conversion will appear in the status box. If there are unconverted logical addresses, they are saved to a file with the extension “.s19.extra”. The unconverted logical addresses might be eeprom which we will discuss in more detail later. This is the output from Log2Phy showing the conversion of a logical file for the MC9S12XDP512. Paged EEPROM Logical addresses are treated as segments of 1KB. These segments (or pages) of memory occupy 0x0800 to 0x0BFF. There is a fixed 1KB block from 0x0C00 to 0x0FFF. For example, the last eeprom page (0xFF) of the MC9S12XDP512 is 0x13FC00 to 0x13FFFF or 0x0C00 to 0x0FFF. The physical address space of the entire eeprom is 0x13F000-0x$13FFFF. Logical records for eeprom must also be converted with Log2Phy. Locate Log2Phy_12_XEE.exe and open the utility. Like before, select your device from the DeviceType drop down box. Select the Logical Record File and the physical S-Record output file. Then press the convert button to generate the S-Record. This is the output from Log2Phy_12_XEE showing the conversion of a logical eeprom file for the MC9S12XDP512. The logical records I used in my example was generated with the following assembly source: ;Example device=9S12XDP512 ;Paged Flash org $018000 ;not in device space dw $0101,$0102,$0103 org $e08000 ;page E0, physical address $780000 dw $e001,$e002,$e003 org $e88000 ;page E8, physical address $7A0000 dw $e801,$e802,$e803 org $f08000 ;page F0, physical address $7C0000 dw $f001,$f002,$f003 org $f88000 ;page F8, physical address $7E0000 dw $f801,$f802,$f803 org $4000 ;page FD, physical address $7F4000 dw $4001,$4002,$4003 org $8000 ;page FE, physical address $7F8000 dw $8001,$8002,$8003 org $c000 ;page FF, physical address $7FC000 dw $c001,$c002,$c003 ;Paged EEPROM org $400 ;not in device space dw $0401,$0402,$0403 org $fc0800 ;page FC, physical address $13F000 dw $fc01,$fc02,$fc03 org $fc0B00 ;page FC, physical address $13F300 dw $fb01,$fb02,$fb03 org $fd0800 ;page FD, physical address $13F400 dw $fd01,$fd02,$fd03 org $fd0b00 ;page FD, physical address $13F700 dw $fd01,$fd02,$fd03 org $fe0800 ;page FE, physical address $13F800 dw $fe01,$fe02,$fe03 org $fe0b00 ;page FE, physical address $13FB00 dw $fe01,$fe02,$fe03 Common Pitfalls 1. Selecting the wrong device selection in the Log2Phy results in incorrect mapping in the PHY. This leads to address out of range errors. 2. Log2Phy is only required for HC(S)12(X) with banked memories. 3. Your linker is configured to add SRAM data into the .s19. PROG-HL-12Z and Log2Phy do not support SRAM addresses. These SRAM addresses will be left unconverted. They will be ignored in the programming software. Conversion Workflow The logical record generated by your compiler toolchain will likely contain the paged flash and eeprom data in the same file. The recommended conversion workflow is: 1. Run Log2Phy_12.exe and convert 9S12XDP512.s19. 2. Log2Phy_12.exe creates 9S12XDP512.phy and 9S12XDP512.s19.extra 9S12XDP512.phy contains the linear Flash addresses 9S12XDP512.s19.extra contains the unconverted paged EEPROM addresses 3. Run Log2Phy_12_XEE.exe and convert 9S12XDP512.s19.extra. 4. Log2Phy_12_XEE.exe creates 9S12XDP512.s19.extra.phy 9S12XDP512.s19.extra.phy contains the linear EEPROM addresses. This bits from the physical address that are used to determine a corresponding logical address, which contains the page index and address in the page window, can be determined from the microcontroller datasheet. This is what is shown for the MC9S12XDP512.
Several HC(S)12(X) microcontroller families such as the HCS12XDP, HCS12XEQ, HCS12XHZ, and others, also support a paged eeprom architecture. These devices treat a 1KB block of memory from $0800 to 0x0BFF as a memory window. This window allows multiple 1KB blocks to be switched into and out of eeprom memory. An 8-bit eeprom page register (EPAGE) tells the microcontroller which block to read.
Converting Addresses from Physical to Logical
