Hardware connections
The following is the minimum set of signals required to access a memory-mapped external flash:

A[X:0] – Address signals
D[Y:0] – Data signals
CS – Chip Select
WE or R/W – Write Enable
OE – Output Enable

How PROG works
PEmicro’s PROG software forces the processor into background (or "debug") mode, where it gains full access to the processor’s resources. The flash programming algorithm is then loaded into the processor’s RAM. The algorithm contains all of the routines necessary to erase and program the external flash.

PROG always moves the external flash so that it begins at address 0 for programming. If your own memory map is different, PROG will need to account for this with the correct base address. 

Accessing the external flash
The PROG software uses the processor to access the external flash. This means that from the processor’s perspective, it must be able to read and write to the external flash. Usually, this is all handled by the processor’s external bus interface. Most of the external flash algorithms provided by PEmicro assume that this configuration is already handled by the user.

For example, most processors automatically start up with CS0 as the global chip select. The processor uses this chip select for all external memory accesses until it is reconfigured by the user. Likewise, the processor checks certain signals during bootup to determine the width of the data bus on CS0.

Extra initialization
Depending on the processor and external flash used, there may be some extra initialization that is not automatically performed by the processor on bootup, but is necessary before flash programming can take place. Users may perform this extra initialization by adding commands to the beginning of the algorithm itself. The algorithms may be edited with a simple text editor such as Notepad. Refer to the PROG help file for more detailed information on these commands.

Some examples:

1) Processor’s internal SRAM needs to be enabled, because it is disabled at bootup
NO_ON_CHIP_RAM
CONTROL=80000001/0C05/             ;set up rambar to place ram at $80000000

2) Processor has a software watchdog that needs to be disabled
WRITE_WORD=0000/40140000/          ;kill extra sw watchdog

3) External bus interface is not properly configured after bootup
WRITE_WORD=0000/40000080/       ;CSAR0 - CS0 at address 0
WRITE_LONG=00000101/40000084/       ;CSMR0 - Enable CS0
WRITE_WORD=3D80/4000008A/       ;CSCR0 16-bit data bus

Troubleshooting
- Make sure you are using the correct algorithm. Please refer to this previous blog post for more information about algorithm selection.
- Double check hardware connections between the processor and the external flash.
- Check if the processor is actually able to access the external flash. The PROG software has a command called “Show Module” which will attempt to read the contents of the flash. If the data is displayed as XX, then the processor was unable to read the external flash.
-  If the hardware connections are good but the processor’s external bus configuration needs tweaking, a debugger will allow you to check the processor’s settings on bootup to make sure they match up with the external flash.