PEmicro Blog

Enabling and Disabling ECC on Cypress PSoC5 Devices

by Gilbert Yap on Mar 21, 2019

Cypress’ PSoC5 line of microcontrollers are a great option for high performance at a low cost. The PSoC 5 provides an Error Correcting Code (ECC) feature to help detect errors in operations that manipulate the flash memory. The ECC peripheral can be enabled or disabled by writing to the Nonvolatile Latch (NVL). The advantage of disabling ECC is that each row of flash gains 32 bytes for data storage, extending the row from 256 to 288 bytes.

The following table outlines how much storage can be gained from disabling ECC based on the device’s flash memory.


Flash Memory Size (KB)

Storage Gained (KB)

64

8

128

16

256

32


When purchasing a new PSoC5 device from Cypress, the ECC feature is enabled by default. Users whose programs use the ECC bytes for program or data storage will be met with an error if they attempt to program this area. These users should use the “DC ;Disable ECC” option in the Cyclone Image Creation Tool or PROGACMP prior to programming their new device. The ECC will be disabled from this point forward, but can be enabled by using the “EC ;Enable ECC” command. 

Tags related to this Blog Post

Cyclone     Cyclone FX     Multilink     Multilink FX     Prog ACMP     ARM     Cypress     Production Programming     Debug