In the case of flash memories connected to the address/data bus of an MCU, it can be difficult to understand when the chip select and/or other control pins are configured properly. Most often the issue is that the external flash memory Chip Enable (~CE), Output Enable (~OE), or Write Enable (WE) signals are not being driven properly. This blog post describes a way to look at these three signals to determine if they are being driven properly.

Different algorithms make different assumptions as to how the flash devices are connected to the MCU. For instance, with a NOR flash connected to a Coldfire MCU via the address/data bus, most PEmicro external algorithms assume that address/data bus signals default to the appropriate functions out of reset, and that the flash's Chip Enable pin is connected to the ColdFire device's Global Boot Chip Select and the flashes' Output Enable and Write Enable pins are both connected to the ColdFire device's “Read, Not Write” pin.

However, there are many other connection configurations, and PEmicro's algorithms can be set up to suit most of them. For example, the configuration can be changed to a non-global chip select, to use multiple chip selects to generate the CE and WE signals, or to enable additional hardware specific enable signals as necessary. WRITE_BYTE, WRITE_WORD, and WRITE_LONG commands (among others) may be added to the programming algorithm header to configure the MCU peripheral registers as needed before programming. Refer to the documentation for more details.

What if the flash doesn't program or read properly during a flash programming session? It is likely a configuration issue. PEmicro's interactive PROG flash programming software has a "Chip Select Diagnostics Mode" to help troubleshoot this scenario. This is useful if the user is able to load the external Flash algorithm but not view the contents of Flash, program it, or erase it. The Diagnostics Mode can verify that the control signals are asserted correctly for Flash operations.

The Diagnostics mode is used in conjunction with an oscilloscope or logic probe so that each control pin can be checked for the proper state when accessing the Flash memory. The probes should be connected directly to the pins on the Flash memory device itself to accurately show the signal states that the flash is receiving. The Diagnostic Mode provides the capability to perform a single 32-bit read or write to the flash memory region. The user can then make sure that the signals on the flash toggle appropriately.

When a write operation is performed, the following should occur: the ~CE (chip enable) of the flash pulses low, the ~WE (write enable) of the flash pulses low, and the ~OE (output enable) of the flash remains high.

When a read operation is performed, the following should occur : the ~CE (chip enable) of the flash pulses low, the ~WE (write enable) of the flash stays high, and the ~OE (output enable) of the flash pulses low.

If the signals do not toggle properly, check whether the chip select region is configured for the proper address range within the MCU (the Diagnostics utility indicates the expected chip select address range) and that all peripherals and pin assignment registers are configured properly.

In the following example, the Diagnostics mode is used to verify the programming algorithm configuration for an AM29LV320DB connected to the CS0 chip select on a NXP ColdFire MCF5272.

The Diagnostics mode is accessed through the tool bar from the ChipSelectDiagnostics option within the interactive flash programming software.

This is the Diagnostics Mode dialog. The chip selects are configured to be active in the address range of $000000 to $3FFFFF. There are two test operations which can be performed on the Flash: WRITE and READ.

Here are the results of the diagnostics on the control signals of the AM29LV320DB connected to a 16 bit data bus.

Below is the waveform that results from performing a WRITE test to the beginning of the Flash. Chip Enable is asserted and then Write Enable is asserted for two pulses. Output Enable remains high. The reason WE is asserted twice is that this particular algorithm has a 16-bit data bus and the test write is 32-bits.

Below is the waveform that results from performing a READ test to the beginning of the Flash. Chip Enable is asserted and then Output Enable is asserted for two pulses. Write Enable remains high.

If the chip selects are not properly configured, the waveforms of each signal will provide some insight into how the algorithm must be modified. New or custom external NOR Flash algorithms may be requested on the PEmicro Flash Programming Algorithms page.