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MC9S08MM128
allen l. migrated on Dec 31, 2013 at 11:00 AM
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  • our customer need for MM128 .S8P Algorithms file.
    beacuse they used flash program for BDM, this can't setting to 31.25Khz.
    we have use version:1.01 ;version 1.01, 12/10/2009, Copyright P&E Microcomputer Systems, www.pemicro.com [9s08mm128]

    than used this version. first program MM128 this ok,but prorgam MM128 again,can't program MM128 and DBM will show "the trim vaule could not be measured properly".
    we trid need used cycle pro standalone erase MM128. can once again program this MCU.

    this we modify and sotred "trim value", will can't program MM128.
    ******************************************
    // Common initialization of the write once registers
    // SOPT1: COPT=3,STOPE=0,BLMSS=0,BKGDPE=1,RSTPE=0
    SOPT1 = 0xC2;
    // SPMSC1: LVDF=0,LVDACK=0,LVDIE=0,LVDRE=1,LVDSE=1,LVDE=1,BGBE=0
    SPMSC1 = 0x1C;
    // SPMSC2: LPR=0,LPRS=0,LPWUI=0,PPDF=0,PPDACK=0,PPDE=1,PPDC=0
    SPMSC2 = 0x02;
    // SPMSC3: LVDV=0,LVWV=0,LVWIE=0
    SPMSC3 &= (unsigned char)~0x38;
    // System clock initialization
    if (*(unsigned char*far)0xFFAF != 0xFF) { // Test if the device trim value is stored on the specified address
    MCGTRM = *(unsigned char*far)0xFFAF; // Initialize MCGTRM register from a non volatile memory
    MCGSC = *(unsigned char*far)0xFFAE; // Initialize MCGSC register from a non volatile memory
    }
    // CCSCTRL: RANGE1=0,HGO1=0,ERCLKEN1=0,OSCINIT1=0,EREFS1=1,EN=0,TEST=0,SEL=0
    CCSCTRL = 0x08; // Configure the XOSC1 clock
    // MCGC2: BDIV=0,RANGE=0,HGO=0,LP=0,EREFS=0,ERCLKEN=0,EREFSTEN=0
    MCGC2 = 0x00; // Set MCGC2 register
    // MCGC1: CLKS=0,RDIV=0,IREFS=1,IRCLKEN=0,IREFSTEN=0
    MCGC1 = 0x04; // Set MCGC1 register
    // MCGC3: LOLIE=0,PLLS=0,CME=0,DIV32=0,VDIV=1
    MCGC3 = 0x01; // Set MCGC3 register
    // MCGC4: DMX32=0,DRST_DRS=2
    MCGC4 = 0x02; // Set MCGC4 register
    while(!MCGSC_LOCK) { // Wait until FLL is locked
    SRS = 0x55; // Reset watchdog counter write 55, AA
    SRS = 0xAA;
    }

    // SOPT2: COPCLKS=0,COPW=0,CLKOUT_EN=0,ACIC=0
    SOPT2 = 0x00;
    // SCGC1: CMT=1,TPM2=1,TPM1=1,ADC=1,DAC=1,IIC=1,SCI2=1,SCI1=1
    SCGC1 = 0xFF;
    // SCGC2: USB=1,PDB=1,IRQ=1,KBI=1,PRACMP=1,TOD=1,SPI2=1,SPI1=1
    SCGC2 = 0xFF;
    // SCGC3: VREF=0,CRC=1,FLS1=1,TRIAMP2=1,TRIAMP1=1,GPOA2=1,GPOA1=1
    SCGC3 = 0x7F;
    // Common initialization of the CPU registers
    // SOPT3: SCI1PS=1,IICPS=0,SCI1_PAD=0
    SOPT3 = (SOPT3 & (unsigned char)~0x22) | (unsigned char)0x40;
    // SIMIPS: RX1IN=0,MTBASE1=0,MODTX1=0
    SIMIPS &= (unsigned char)~0x4D;

    TODC_TODCLKS = 0b00;   //OSCOUT clk
    TODC_TODPS = 0b001;   //32.768kHz
    TODC_TODCLKEN = 1;   //enable TOD clock output
    TODC_TODR = 1; //reset counter
    ******************************************





    Comments

  • Hello Allen,

    What software toolset are you using? It seems like you are working with Codewarrior. If that is the case, what Codewarrior version are you using?

    Please describe your step by step hardware/software setup procedure and indicate the exact place where the failure takes place.

    Please open a support request on our website with a note to address it to attention of Zahar Raskin. Please attach a copy of project that you are working with, as well as a FLASH programming algorithm that is being used by your software.

    http://www.pemicro.com/support/index.cfm" target="_blank">http://www.pemicro.com/support/index.cfm

    Best Regards,
    Zahar
    P&E





    QUOTE (allen @ Nov 28 2010, 09:24 PM) [legacy comment]
    our customer need for MM128 .S8P Algorithms file.
    beacuse they used flash program for BDM, this can't setting to 31.25Khz.
    we have use version:1.01 ;version 1.01, 12/10/2009, Copyright P&E Microcomputer Systems, www.pemicro.com [9s08mm128]

    than used this version. first program MM128 this ok,but prorgam MM128 again,can't program MM128 and DBM will show "the trim vaule could not be measured properly".
    we trid need used cycle pro standalone erase MM128. can once again program this MCU.

    this we modify and sotred "trim value", will can't program MM128.
    ******************************************
    // Common initialization of the write once registers
    // SOPT1: COPT=3,STOPE=0,BLMSS=0,BKGDPE=1,RSTPE=0
    SOPT1 = 0xC2;
    // SPMSC1: LVDF=0,LVDACK=0,LVDIE=0,LVDRE=1,LVDSE=1,LVDE=1,BGBE=0
    SPMSC1 = 0x1C;
    // SPMSC2: LPR=0,LPRS=0,LPWUI=0,PPDF=0,PPDACK=0,PPDE=1,PPDC=0
    SPMSC2 = 0x02;
    // SPMSC3: LVDV=0,LVWV=0,LVWIE=0
    SPMSC3 &= (unsigned char)~0x38;
    // System clock initialization
    if (*(unsigned char*far)0xFFAF != 0xFF) { // Test if the device trim value is stored on the specified address
    MCGTRM = *(unsigned char*far)0xFFAF; // Initialize MCGTRM register from a non volatile memory
    MCGSC = *(unsigned char*far)0xFFAE; // Initialize MCGSC register from a non volatile memory
    }
    // CCSCTRL: RANGE1=0,HGO1=0,ERCLKEN1=0,OSCINIT1=0,EREFS1=1,EN=0,TEST=0,SEL=0
    CCSCTRL = 0x08; // Configure the XOSC1 clock
    // MCGC2: BDIV=0,RANGE=0,HGO=0,LP=0,EREFS=0,ERCLKEN=0,EREFSTEN=0
    MCGC2 = 0x00; // Set MCGC2 register
    // MCGC1: CLKS=0,RDIV=0,IREFS=1,IRCLKEN=0,IREFSTEN=0
    MCGC1 = 0x04; // Set MCGC1 register
    // MCGC3: LOLIE=0,PLLS=0,CME=0,DIV32=0,VDIV=1
    MCGC3 = 0x01; // Set MCGC3 register
    // MCGC4: DMX32=0,DRST_DRS=2
    MCGC4 = 0x02; // Set MCGC4 register
    while(!MCGSC_LOCK) { // Wait until FLL is locked
    SRS = 0x55; // Reset watchdog counter write 55, AA
    SRS = 0xAA;
    }

    // SOPT2: COPCLKS=0,COPW=0,CLKOUT_EN=0,ACIC=0
    SOPT2 = 0x00;
    // SCGC1: CMT=1,TPM2=1,TPM1=1,ADC=1,DAC=1,IIC=1,SCI2=1,SCI1=1
    SCGC1 = 0xFF;
    // SCGC2: USB=1,PDB=1,IRQ=1,KBI=1,PRACMP=1,TOD=1,SPI2=1,SPI1=1
    SCGC2 = 0xFF;
    // SCGC3: VREF=0,CRC=1,FLS1=1,TRIAMP2=1,TRIAMP1=1,GPOA2=1,GPOA1=1
    SCGC3 = 0x7F;
    // Common initialization of the CPU registers
    // SOPT3: SCI1PS=1,IICPS=0,SCI1_PAD=0
    SOPT3 = (SOPT3 & (unsigned char)~0x22) | (unsigned char)0x40;
    // SIMIPS: RX1IN=0,MTBASE1=0,MODTX1=0
    SIMIPS &= (unsigned char)~0x4D;

    TODC_TODCLKS = 0b00;   //OSCOUT clk
    TODC_TODPS = 0b001;   //32.768kHz
    TODC_TODCLKEN = 1;   //enable TOD clock output
    TODC_TODR = 1; //reset counter
    ******************************************



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