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FAQ ID # 222
 
Question
I am having sporadic failures trying to debug my Kinetis microprocessor with a USB-ML-Universal hardware interface due to some ringing on CLK line. What can be done to address this issue?
 
Answer
On some Kinetis board designs a few cases were reported of sporadic communication issues due to the ringing and signal overshoot on SWDCLK clock line. This issue will be addressed on all USB-ML-UNIVERSAL multilinks starting with October, 2015 build and then moving forward. To modify the Multilink Universal to improve the SWDCLK termination, our recommendation is to replace the R30 resistor with: RES 47 OHM 1/10W 5% 0603 SMD
 
Related Downloads
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Architectures Categories Products
General / Miscellaneous, Interface Hardware/Cable, Debugger, Flash Programming Software, Development Kit / Package USB-ML-UNIVERSAL
 
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