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Flash Algorithms For ARM devices, SPI External Flash

P&E’s SPI serial programming algorithms have been tested on ARM Cortex-M0, M0+, M3, and M4 controllers from various P&E-supported vendors. They should also work on other ARM processors which have the same minimum instruction set and debug interface. In addition to this basic requirement, the Cortex-M microcontroller connected to the external memory must have a minimum of 2 kB of RAM to load and then execute the programming routines.

View List (Freescale, STMicroelectronics, TI, etc.): P&E Serial SPI Memory Programming Algorithms (Archive 1)

View List (NXP): P&E Serial SPI Memory Programming Algorithms (Archive 2)

P&E’s SPI serial algorithms are designed to use any four I/O port pins on the controller to talk to SPI serial memory devices (by default we do not make use of the SPI peripheral). This makes it easy for the user to configure these algorithms for their particular hardware set up. The user simply specifies the port addresses and pin numbers for each of the four SPI interface signals. The user configures their device using 8-, 16-, and 32-bit memory write commands that are inserted into the programming algorithm header. These commands are used to turn off the watchdog, set up the clock, and turn on and initialize I/O pins. The information required to do this is readily available from the code used to configure the device during normal operation. Examples of this procedure are included in P&E's serial SPI programming manual which can be downloaded here:

User Guide: P&E Serial SPI Memory Programming for ARM devices (.pdf)

The SPI programming algorithms are divided into two separate archives, one for NXP LPC ARM devices and one for the other P&E-supported manufacturers (Freescale, STMicroelectronics, TI, etc.). The reason that there are two separate archives is that the NXP LPC devices have RAM at address 10000000, whereas the rest have RAM at address 20000000. The archives may be downloaded here:

SPI Algorithm Archive 1 (Freescale, STMicroelectronics, TI, etc.): Click to Download Archive

SPI Algorithm Archive 2 (NXP LPC): Click to Download Archive

All of the algorithms supplied by P&E for programming SPI memory devices automatically verify that the data is programmed properly during the programming process, hence it is not necessary to do a separate verify command. However, a separate verify command is still available if desired.

The algorithms can be used in P&E’s PROG software and P&E's Cyclone stand-alone programmers. Support for these algorithms in P&E’s GDB server is planned.

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