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BOSTON - June 16, 2016 - P&E Microcomputer Systems, Inc. today announced the ability to add usage restrictions to programming images created for the Cyclone FX stand alone programmer. These usage restrictions include the ability to limit programming to a specific date range and also to set a maximum number of programming operations which can occur. The effect of this is that the user can limit the duration and amount of programming allowed by an image. This can be useful for protecting the IP contained within a programming image as well as making sure that programming images in production are not too far out of date. These restrictions persist even when the images are deleted/restored on a Cyclone unit's internal memory or SD card. Images are encoded in such a way as to deter tampering.

Image restrictions are set in the Cyclone Configuration Utility

The Cyclone FX programmer is a stand-alone in-circuit programmer which supports many NXP and ARM Cortex based devices. Cyclone FX owners who wish to update their Cyclones can download the latest software and firmware from P&E's website.

Programming count displayed on the Cyclone FX home screen

This new security feature is documented in the latest version of the Cyclone FX User Manual.


BOSTON – March 15, 2016 - P&E Microcomputer Systems is now shipping the Cyclone Universal FX, which is the flagship model of P&E's next-generation Cyclone programmers. P&E's Cyclones have set the standard for powerful, versatile production programming and debug. The Cyclone Universal FX was designed to offer the very best of the Cyclone platform with a focus on enhanced security, extremely fast performance, test, and expandability.

The Cyclone Universal FX combines support for many NXP 8-/16-/32-bit architectures with support for ARM® Cortex® devices from many different manufacturers. P&E has maintained compatibility with their existing product line while combining support for all of these target architectures into a single unit.

Cyclone Universal FX Features:

(Features in bold are key differentiators between the Cyclone Universal and Cyclone Universal FX
  • 4.3" Touchscreen Display
  • Start button rated for 1M+ presses
  • Secure: Anti-tamper technology, internal memory protection & encryption. Advanced security features coming soon.
  • Extremely fast: Up to 25Mb/s target communications speed
  • 1GB internal memory
  • No practical limit to number of programming images
  • Memory expansion via SD card
  • USB Expansion Port and Control Expansion Port features coming soon
  • Provides/switches target power
  • Runs test/calibration applications
  • Simple to control/automate
  • Stores multiple programming images
  • Ethernet, USB, & Serial
  • Can operate in stand-alone mode or integrated with a PC
  • Multiple units can operate together as a gang programmer
  • and many more!

Read more on the Cyclone Universal FX product page.

ARM and Cortex are registered trademarks of ARM Limited or its subsidiaries.

Supported Architectures

  • Kinetis®
  • S32
  • LPCxxxx
  • ColdFire® V2/V3/V4
  • ColdFire+/V1
  • MPC5xx/8xx
  • Qorivva® (MPC5xxx, SPC5xxx)
  • DSC
  • MAC7xxx
  • S12Z
  • HC(S)12(X)
  • HCS08
  • HC08
  • RS08
  • ARM® Cortex® processors

BOSTON, MA – July 14, 2015 - Following their debut at the 2015 Freescale Technology Forum, P&E's soon-to-be-released Cyclone Universal and Cyclone Universal FX are now available to pre-order. Production quantitites of both new Cyclone programmers are expected to ship by Sept. 15 (subject to change). Those interested in placing a pre-order or simply reviewing the features of our next-generation production programming, test, and debug interfaces may do so at the Cyclones' P&E product page. These new Cyclones each support many architectures and offer impressive feature sets that may include:

  • Large internal memory: 1GB+ secure memory storage.
  • Focus on security: Internal memory protection & encryption, anti-tampering technology, tie images to specific Cyclones, programming count limits, date range limits, logging, etc.
  • Extremely fast target communications: 25mb/s+
  • Enhanced Interface: 4.3" Touch Screen, 1M touch Start Button.
  • External memory: SDHC port for external memory cards
  • Test Support: Images can run test code before programming
  • And more! Launch port, battery backed clock, provides and switches power to target, expanded architecture support, bar code scanner support, current & voltage measurement, etc.

Join Us On Facebook & Twitter

Like us on Facebook and follow us on Twitter for the latest news about the upcoming release of the Cyclone Universal & Cyclone Universal FX.

Click to pre-order, or to learn more about the Cyclone Universal & Cyclone Universal FX.

ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries).
Freescale, Qorivva, Kinetis, and ColdFire are registered trademarks of Freescale Semiconductor, Inc.

Supported Architectures

  • Kinetis®
  • S32
  • LPCxxxx
  • ColdFire® V2/V3/V4
  • ColdFire+/V1
  • MPC5xx/8xx
  • Qorivva® (MPC5xxx, SPC5xxx)
  • DSC
  • MAC7xxx
  • S12Z
  • HC(S)12(X)
  • HCS08
  • HC08
  • RS08
  • ARM® Cortex® processors

AUSTIN, TX – June 22, 2015 - P&E's Cyclones have set the standard for powerful, versatile production programming and debug. We have completely redesigned the Cyclone Platform with state of the art, high-speed technology. We have maintained compatibility with our existing product line while combining support for many target architectures in a single unit and focusing on outstanding security, performance, and features.

Join us at the Freescale® Technology Forum (FTF) in Austin, June 22-25. Come visit us at booth #617 for a chance to win one of two Cyclone Universal FX units, once they are released!

In addition to supporting more target architectures, these new Cyclones offer several improvements over their predecessors:

  • Large internal memory: 1GB+ secure memory storage.
  • Focus on security: Internal memory protection & encryption, anti-tampering technology, tie images to specific Cyclones, programming count limits, date range limits, logging, etc.
  • Extremely fast target communications: 25mb/s+
  • Enhanced Interface: 4.3" Touch Screen, 1M touch Start Button.
  • External memory: SDHC port for external memory cards
  • Test Support: Images can run test code before programming
  • And more! Launch port, battery backed clock, provides and switches power to target, expanded architecture support, bar code scanner support, current & voltage measurement, etc.

Join Us On Facebook & Twitter

Like us on Facebook and follow us on Twitter for the latest news about the upcoming release of the Cyclone Universal & Cyclone Universal FX.

Click to learn more about the Cyclone Universal & Cyclone Universal FX.

ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries).
Freescale, Qorivva, Kinetis, and ColdFire are registered trademarks of Freescale Semiconductor, Inc.

BOSTON – August 27, 2014 - P&E Microcomputer Systems announced the addition of support for Freescale's MPC5xx/8xx devices devices to its high-speed Multilink Universal FX development interface. This addition enhances the all-in-one capabilities of the Multilink Universal FX - P&E's flagship Multilink interface - and solidifies P&E's future support for Freescale's MPC5xx/8xx architecture.

Multilink Universal FX users may download the updated Technical Summary (v.1.03) from P&E's support center.

P&E continues to expand on its line of all-in-one interfaces with the launch of the high-speed USB Multilink Universal FX. Like P&E's original all-in-one interface, the USB Multilink Universal, the new USB Multilink Universal FX supports a varirety of Freescale MCUs, including: Kinetis, Qorivva 55xx/56xx, ColdFire V1/ColdFire+ V1, ColdFire V2-4, HC(S)12(X), HCS08, RS08, Power Architecture PX Series, and DSC. However the new FX interface can download at speeds up to 10x faster and can provide power to the target processor, among other enhancements.

The new USB Multilink Universal FX is natively supported by recent versions of CodeWarrior®, current P&E software applications, and toolchains from many Freescale partners including Keil and Cosmic.

More information about the USB Multilink Universal FX is available on the product page at P&E's website.


We're pleased to announce the release of our latest device drivers. This update includes support for Microsoft Windows XP, Vista, and Windows 7 Operating Systems for both 32-bit and 64-bit architectures, as well as some minor bug fixes.

To get started using the drivers:

  1.     Download P&E Hardware Interface Drivers 10
  2.     Run the file drivers_10_install.exe. If you have an older version of our drivers installed, the setup will automatically perform the update.

NOTE: The latest drivers no longer include support for Windows 98 and ME, but P&E will continue to make our older drivers available. Support for PCI devices (e.g., BDM Lightning) and Parallel port devices has been removed for Windows Vista and later, as well as all 64-bit operating systems.

P&E drivers allow P&E applications to communicate with P&E hardware via the parallel port, PCI bus, Ethernet, Serial, and USB.

This video gives a demonstration of how to load a programming image onto a CompactFlash card in the expansion port of P&E's Cyclone products. CompactFlash activation is a powerful feature that lets users expand the memory and versatility of their Cyclone:


P&E’s PROG programming software will sometimes prompt the user to enter a “Base Address”. In this article, we discuss what the base address is and why it exists.

On most 8-bit and 16-bit processors, the internal flash/eeprom is located at fixed address locations. If this is the case, the associated programming algorithm will NOT prompt the user for a base address, since the address is fixed and already known.

On 32-bit processors and any systems using external flash, the address of the flash may be configured to reside anywhere within the processor’s address space. The developer will decide on an appropriate memory map early in the design process.

For these situations where the flash can be relocated, the PROG software will always move the flash so that it begins at address 0.  However, the developer may not have an object file that matches this new memory mapping. To account for this, the “Base Address” (specified by the user) is subtracted from all addresses in the object file prior to programming.

Below is an example of how the developer’s memory map may differ from the one in PROG. Although the external flash is located at different addresses, it refers to the same physical memory. Here, the user would specify a base address of FFC00000.

The base address should always be the starting address of flash in the developer’s memory map, and not the “first” address where data exists (although in most cases they are the same!)

Today's tip concerns P&E's Cyclone automated programmers. With the release of the Cyclone Automated Control Package, users have been inquiring if there is a way to automate the creation of stand-alone images. Fortunately, with the standard Cyclone PRO/MAX installations, users already have command-line executables that can accomplish this task.

For each architecture there is a corresponding CSAPXXXX.EXE application that can be used to create a stand-alone image file. For example, to create an image for the Coldfire V2/V3/V4 devices, the user would use CSAPBDMCFZ.EXE. For this blog, we will demonstrate how to create a stand-alone image for a 9S08QE128 device by using CSAPHCS08Z.EXE.

Begin by creating a stand-alone configuration file. You can create a configuration file by configuring the programming sequence in the Cyclone Image Creation Utility and then saving it thorugh File ->Save Cyclone Configuration. You can also create a configuration file by using a text editor, typing in the commands, and saving it as a .CFG file. A typical configuration file might use the following sequence:

CM  C:pemicrocyclone_proAlgorithmsHCS089S08QE128.S8P
SS   C: esthcs089S08QE128.S19
EM  ;Erase Module
BM  ;Blank Check Module
PT  ;Program Trim
PM  ;Program Module
VM  ;Verify Module
VC  ;Verify Checksum

In this example, we will save the .CFG file as "9S08QE128.CFG" in c:. With the configuration file created, we can now create a stand-alone image or .SAP file by using the command prompt. In the command prompt, we can invoke the configuration script file as follows:

c:pemicrocyclone_procsaphcs08z.exe "c:9S08QE128.cfg" imagefile "c:9s08qe128.sap" imagecontent "9S08QE128_1_26_2009"

The first parameter, "c:9S08QE128.cfg", specifies the location of the input configuration file.

The second parameter, imagefile  "c:9s08qe128.sap", specifies the name and output location of the .SAP file.

The last parameter, imagecontent "9S08QE128_1_26_2009", specifies the image description.

You can use the '?' character option to cause the utility to wait and display the result of the configuration in the CSAP window. You can also use the '!' character option to cause the utility to wat and display the result only if the file failed to generate.

After invoking the configuration script in the command prompt, the file 9S08qe128.sap is generated in the C: directory. The 9s08qe128.sap file can now be loaded into the Cyclone PRO/MAX by using the Cyclone Automated Control Package or the Cyclone Manage Images Utility.










When you need to convert between object file formats, download one of P&E's free, C language development kits.  These kits include a full GNU compiler toolchain, including Binutils OBJCOPY.

Download PKGPPCNEXUS Starter Edition

Download PKGCFZ_PRO Starter Edition

P&E's ICD In-circuit Debugger and PROG Flash Programmer software, included with the Starter Editions, natively supports several object file formats, including s-record and ELF.  Soon, P&E software will natively support Intel Hexadecimal files.

After installing one of the Starter Editions, run OBJCOPY from the Windows command-line.  The program is located in the gnuin subdirectory within the installation directory.  View the help screen for OBJCOPY from the command-line by typing  "powerpc-eabispe-objcopy" or "m68k-elf-objcopy".  You will see a list of all program options.  To determine which formats are available with OBJCOPY, take note of the final lines of the help screen.  You will use these format names, BFD names, when running OBJCOPY.

To convert a file, use the  "-O" option followed by the name of the desired output format.  The input format may be specified with the "-I" option, though this is often unnecessary.   For example, to convert the object data in a COFF file "file1.coff" to an s-record file "file1.srec":

m68k-elf-objcopy -I coff-m68k -O srec file1.coff file1.srec


powerpc-eabispe-objcopy -I aixcoff-rs6000 -O srec file1.coff file1.srec

If you are looking for greater control of file conversion, look at the options on the OBJCOPY help screen.  For example, with powerpc-eabispe-objcopy you may specify s-record length, force S3 records, and manipulate the linker sections in object files.

Cyclone ACP, Rev. C P&E’s product line of Cyclone stand-alone programmers provides a fast, robust, and automated solution for production-scale programming of microprocessors. However, production facilities may desire an even higher level of automation than the single-button touch capability that is offered by the Cyclone. P&E offers several means of automating control, including a command-line executable, UDP/Serial communications, or the .DLL included in P&E's new Cyclone Automated Control Software Package. In this article, we discuss automated control using the automated control package and the unprecedented level of power and flexibility that it offers.

1.) Introduction – Controlling a Cyclone through the PC

P&E’s new Cyclone Automated Control Package provides the developer with a dynamic link library (DLL) and supporting documentation to allow custom software applications to directly control the Cyclone.

By storing the binary data information, algorithm information, and settings directly into the FLASH memory of the Cyclone, programming operations can be initiated by the simple push of a button. However, the DLL enables us to use the PC to issue a command to the Cyclone to start the same programming sequence!

The use of a PC to control the Cyclone enhances the functionality of the stand-alone programming operations, but also introduces new capabilities that were not available previously. In the following sections, we explore the features of the Cyclone Automated Control Package and present practical examples of how to use it in your own production line.

2.) Setup – Image Creation

The first step is always to create the actual stand-alone images that will be stored onto the Cyclone. These images contain the algorithm needed to program FLASH / EEPROM, the actual binary data to be programmed, the sequence of programming operations, and many user-specified Cyclone settings. P&E’s “Cyclone Image Creation Utility” allows the user to properly configure the stand-alone images.

Above is a screenshot of the dialog in the Cyclone Image Creation Utility which allows the user to configure the stand-alone image. The field on the right shows the programming steps and also the order in which these steps execute.

1.)    First, we select the appropriate algorithm for our processor. In this example, we are using the Freescale HC9S08GB60.

2.)    Next, we specify the target object file that represents the binary data to be programmed into the processor’s FLASH memory. Here, we are using a Motorola S-record file.

3.)    Once the algorithm and the target object file are specified, we are ready to begin programming. Typically, the procedure is to erase the device to make sure it’s blank, program the target, and verify that the contents were written correctly.

In addition to the programming sequence, there are also settings for the Cyclone that we can configure. In the above screenshot, we are using the Cyclone PRO’s power relays to provide the appropriate voltage to power up our processor. This way, we do not need a separate power supply for our target board, simplifying our production line.

Finally, we specify the Image Description so that we can easily identify the image later on. By using the “Store Image to Disk” option, we are able to save this image and its configuration as a .SAP file for future use.

3.) Using the DLL – Simple Example


The above code example shows the most basic operation that is supported by the Cyclone Automated Control Package. Below are the steps we have taken:

Step 1: Contact the desired Cyclone by specifying its IP address. The handle of the Cyclone is returned, and is used to identify the Cyclone in all subsequent function calls.

Step 2: Send a command to the Cyclone to begin the programming operations specified in image #1. These operations were specified during the image creation process.

Step 3: Wait for the Cyclone to complete the programming operations before proceeding.

Step 4: Check to see if any errors occurred during programming and provide a message to the user.

Step 5: Terminate the current session with the Cyclone.

4.) Using the DLL – More Advanced Operations

Programming a serial number



Note: The following are placeholder functions used to simplify the example, and are not provided by the automated control package:




The above example code is an event handler written for a visual MFC application, which is executed each time a button is pressed by the user. Here, we again instruct the Cyclone to perform the stand-alone programming operations of the image stored on the Cyclone. Afterwards, we program a dynamic 2-byte serial number into address 0x100 of the target processor. The serial number is then incremented and written back to a file for later use.

Although there are many different ways to program a serial number without needing to use the automated control package at all, this code example can easily be modified to program dynamic data that is not sequential. For example, if we wish to program the current date or a lot number, using the automated control package and writing your own custom application is by far the easiest and most automated way to accomplish this task.


Automatically update image stored on the Cyclone



This is a very simple example of how to ensure that the image stored on a Cyclone is always up to date. A comparison is performed between the image which currently resides on the Cyclone and an image file at a specified location on the host PC. If there is a mismatch, then we update the image. Afterwards, we proceed with the normal programming operations as seen in the previous examples.

5.) Can I Control Multiple Cyclones?

 Up until now, we have discussed some uses of the Cyclone Automated Control Package with a single Cyclone unit. Since the host PC only sends minimal control information to control each Cyclone, a single PC is actually capable of controlling many Cyclone units simultaneously.


Here, we begin programming operations on 3 separate Cyclone units and wait for their completion before proceeding. In essence, we are programming 3 separate devices in parallel. This can be easily extended to 10, 100, or even 1000 Cyclone units controlled in parallel from a single host PC!

6.) More Examples

Here are a few more real world examples:

·         Quality Control : automatically record statistics on the number of devices that fail during programming.

·         You’re a developer and just completed the firmware development for a brand new product. Now you need to get your production facility up to speed, but they are halfway across the country. Streamline this process by writing a simple application that will add a new image to the Cyclone. Send this along with the new stand-alone image SAP file and you’re done.

·         You use multiple Cyclone units for programming your devices in parallel. Each Cyclone has 4 different images, one for each of your 4 different products. Write an application that allows the user to automatically select the correct image for the current production run.

7.) Conclusion

 Whether you are performing small production runs in-house or programming a large number of chips in a high-volume facility, P&E’s Cyclone product family provides a powerful, yet affordable, solution. With the advanced parallel programming, image management, and error tracking features provided by P&E’s new Cyclone Automated Control Package, you now have the power to completely automate your production programming process like never before.

For more information, see also:

ICDPPCNEXUS, P&E’s in-circuit debugger for the MPC55xx/MPC56xx processors, uses reset scripts to properly initialize the device when it comes out of reset. When these devices power on normally, the Boot Assist Module (BAM) automatically performs a default startup initialization.

However, if the processor is forced into debug mode, the BAM does not execute. Because of this, many of the processor’s resources, such as internal FLASH and internal SRAM, are not available until a proper reset initialization is manually executed. The ICDPPCNEXUS debugger uses reset script files to specify the exact initialization that should be performed immediately after the processor is reset and debug mode is entered.

ICDPPCNEXUS includes a set of these reset script files which initialize the processors with a standard configuration. These files have a .mac extension and can be viewed/edited with a standard ASCII editor such as Windows Notepad. Let’s take a look at some of these script files in more detail:

These commands set up an entry in the MMU to map the internal SRAM to begin at address 0x4000_0000. This is accomplished by writing to the MMU Assist Registers (MAS0 – MAS3) and then executing the “tlbwe” instruction. This type of setup is typically repeated for internal FLASH and peripheral modules.

Fatal errors can occur if an interrupt is triggered and the interrupt vector address points to an invalid memory region. The above commands configure vector addresses to point to the beginning of SRAM, which is a valid address.

This command initializes SRAM from 0x4000_0000 to 0x4000_FFFF by writing random data to this entire memory region.

The last example above is device specific. The SWT watchdog is disabled by writing a 0xFF00_000A to address 0xFFF3_8000. The core watchdog is also disabled by writing a 0 to SPR 340.

In a previous post, we showed how to use PKGPPCNEXUS and  PKGCFZ_PRO to display the contents of an ELF/DWARF file using Readelf.  In this post, we look at the Readelf output and explain its description of your object code. 

We will use this example Readelf output to illustrate the kinds of information that Readelf provides.

The first item of interest is labeled "Entry point address". This is the address of the first instruction executed after reset. Your compiler or linker determines this value. The P&E debugger optionally uses the entry point address to execute your target application.

The "Section Headers" portion lists all of your linker sections that made it to your ELF/DWARF file. The ".debug_info" section is where ICD looks for the debugging information entries. Note that not all of these sections contribute to the application memory map.

The portions titled "Program Headers" and "Section to Segment mapping" describe the application memory map. ICD and PROG use the program headers to determine where to place object code on your target. Check that a linker section is included in the final memory map by examining the section to segment mapping. Note that the first entry in the program headers corresponds to the first entry in the section to segment mapping.

From the program headers, you can gather the following information about the memory map:
Type - Only LOAD types contribute to the final memory image
VirtAddr - load time location of code
MemSiz - number of bytes that the code segment occupies in the final memory image

P&E's PROG and ICD software support an uncommon feature of the GNU compiler.  GCC uses both the program header VirtAddr and PhysAddr fields, the former for run time address and the latter for load time address.  For more information on this useful feature, please refer to this document.

Did you know you can safeguard data while erasing your Flash/EEPROM module during programming? P&E has added a “preserve range” function that can be used in a programming algorithm to preserve memory ranges. The function looks at the range to be preserved, saves it, and restores it after the Flash/EEPROM has been erased. The user can easily preserve code segments stored in flash with a couple of modifications to the header of the programming algorithm.

A flash programming algorithm is a text file which describes how a particular flash block is to be programmed. The algorithm contains a configuration section as well as some s-record data which implements the programming process. User's commonly will modify the configuration section to change the behavior of the programming algorithm, such as to add ranges of data to preserve.

Flash algorithms describe flash blocks as having either a fixed address (common for internal flash on a microcontroller) or a variable address (common for flash chips external to a microprocessor). Algorithms which do not have a fixed address for the flash will prompt the user for the base address of the flash at the time of programming. In either case, the algorithm can be used to specify ranges of flash to preserve relative to the start of the flash block.

For an algorithm with a fixed address for the flash block, the following line will indicate the flash block location:

NO_BASE_ADDRESS=NNNNNNNN/     ; NNNNNNNN is a Hexadecimal value indicating the start of flash

Do not modify the NO_BASE_ADDRESS line! You are simply going to add some lines after it which indicate that you wish to preserve certain ranges relative to the base address. The configuration line(s) you should add directly after the NO_BASE_ADDRESS line should have the following format (very strictly formatted - no spaces allowed and include all forward slashes):

PRESERVE_RANGE=SSSSSSSS/EEEEEEEE/     ; SSSSSSSS is the starting offset, EEEEEEEE is ending offset

Adding this line would preserve the following memory range : NNNNNNNN+SSSSSSSS to NNNNNNNN+EEEEEEEE.


If there was an algorithm which was designed to program a flash block with address range $4000-$FFFF, you would see the following configuration in the flash algorithm:

NO_BASE_ADDRESS=00004000/         ;Fixed at $4000
ADDR_RANGE=00000000/0000BFFF/00/FFFFFFC0/FFFFFE00/     ; $4000-$FFFF


Do not modify these lines! If you wanted to preserve a certain memory range, you would specify it after the line with the NO_BASE_ADDRESS command (which sets the base address) and before the lines with ADDR_RANGE. If you wanted to preserve the memory from address $F000-$F001, you would add the bolded line as follows:

NO_BASE_ADDRESS=00004000/         ;Fixed at $4000
PRESERVE_RANGE=0000B000/0000B001/ ; Preserve $0000F000-$0000F001
ADDR_RANGE=00000000/0000BFFF/00/FFFFFFC0/FFFFFE00/ ; $4000-$FFFF

Note that the preserve_range command requires the offset from the base address of your memory. If you add $4000 to $B000 and $B001, you have $F000 and $F001.

In addition, this functionality does not limit the user to preserving only 1 range or one address. The function can be called several times in the algorithm if several ranges and/or addresses need to be preserved, or if the Flash/EEPROM is segmented into several fields or extended into pages.


For the flash block above (from $4000 to $FFFF), if the user wished to preserve addresses $5001, $5006 and ranges $CCAA-$CCBB and $D123-$DFFF, the following segment would be added to the algorithm:

NO_BASE_ADDRESS=00004000/         ;Fixed at $4000
PRESERVE_RANGE=00001001/00001001/ ; 5001-4000
PRESERVE_RANGE=00001006/00001006/ ; 5006-4000
PRESERVE_RANGE=00008CAA/00008CBB/ ; CCAA-4000/CCBB-4000
PRESERVE_RANGE=00009123/00009FFF/ ; D123-4000/DFFF-4000
ADDR_RANGE=00000000/0000BFFF/00/FFFFFFC0/FFFFFE00/ ; $4000-$FFFF


It is also possible to preserve several different segments across different pages of Flash/EEPROM. The user should know how to access each page of memory logically in the software. Let's look at the HCS08 AC128. The paged Flash memory can be accessed with the following ranges. This will typcially be described in the configuration section of the programming algorithm.

$08000-$0BFFF --> Page 0
$18000-$1BFFF --> Page 1
$28000-$2BFFF --> Page 2 
$38000-$3BFFF --> Page 3 

If the user wanted to preserve memory on page 0 from $08000-$08005 and on page 3 from $38000-$38005, he would add the following commands :

NO_BASE_ADDRESS=000020F0/         ;Fixed at $20F0
PRESERVE_RANGE=00005F10/00005F15/ ; Preserve $08000-$08005
PRESERVE_RANGE=00035F10/00035F15/ ; Preserve $38000-$38005
ADDR_RANGE=00000000/0000DF0F/00/FFFFFFC0/FFFFFE00/ ; $20F0-$FFFF

Note again that the offset $20F0 is added to the parameters of the command to calculate the correct paged memory ranges to preserve. Add $20F0 to $5F10 to get $08000 and add $20F0 to $35F10 to get $38000.  

The PROG software will report a checksum error and warn that the algorithm has been modified. This error can be ignored. If you wish to remove the warning, please use our command-line ADDCRC utility to update the checksum.

The Blank Check command will now fail because of the preserved data. Also note that the Verify Module command will ignore the addresses that are preserved when comparing memory against an S-record.

Any information which follows a semicolon (;) on a configuration line is a comment.

P&E can provide more a detailed specification of flash algorithm construction upon request.

P&E has added a new Chip Select Diagnostic mode to its interactive flash programmers to allow the user to diagnose memory map configuration problems.

P&E’s flash programmers support an extensive array of external flash devices connected to the processor. P&E’s algorithms are designed to work by default when the flash device is connected to the boot chip select and no modification is needed to the reset configuration of the output enable and write enable lines. However, there are numerous ways in which the flash can be connected that may require changes to the default reset configuration of the processor’s chip select, write enable, and output enable operation.

When another configuration is used, the algorithm may require some modification to work.  This often involves writing to the chip select registers to change which chip select is used, to make certain chip selects read only or write only, or to change the base address of the chip select. P&E’s algorithms expect the flash to be located at a specific location in the memory map. This location is listed in the algorithm itself as a comment. An example can be seen here:

;begin_cs device=$00000000, length=$00800000, ram=$10000000

This line indicates that the flash must be configured to be in the memory map at address 0, and that the full range $00000000-$00800000 must be configured to address the flash. This is separate from the “Base Address” capability in the programmer user interface which makes the flash appear to be anywhere the user selects it (internally it physically resides at a specific location).

On many devices the boot chip select is enabled everywhere. If a configuration change is needed, there are many commands which allow the registers on the device to be written during startup. The WRITE_LONG, WRITE_WORD, and WRITE_BYTE commands are examples of commands which can be used to write to memory mapped registers. There are also commands on some architectures to allow the configuration of where the registers are located, such as the CONTROL command on the ColdFire architecture. Here is an example of initializing the CS1 chip select on a 5272 device instead of the default CS0 chip select (the boot chip select).

CONTROL=20000001/0C0F/           ;set mbar on with address $20000000
WRITE_LONG=00000000/20000040/    ;cs0 off
WRITE_LONG=00000201/20000048/    ;proc=5272 cs=CS1 16 bits, r/w
WRITE_LONG=00000078/2000004C/    ;proc=5272 cs=CS1 on

The question often comes up : How do I know my chip select configuration is correct?

P&E has added a diagnostic tool to it’s interactive flash programmers which allow the user to test the chip select configuration to make sure the chip select, write enable, and output enable signals have been properly configured. The utility may be chosen from the “ChipSelectsDiagnostic” selection on the main menu bar. A portion of the utility is shown here:

Chip Selects Diagnostics

The user will need a scope or a logic probe to see if the signals maintain the proper state during the test read and test write functions. Setting the chip select registers properly solves the majority of support questions P&E receives regarding external flash algorithms.

New flash algorithms may be requested on P&E’s Flash Programming Algorithms page.

P&E's Cyclone programmers are sophisticated and flexible tools designed for in-circuit flash programming.  Field service updates, an important part of a field system, often occur in places where there is no access to a PC or power outlet.  However, P&E's Cyclones are lightweight, compact programmers that have been designed to operate in stand-alone mode – i.e. they can be loaded with a programming image, detached from the PC, and then be controlled via the LCD menu and control buttons. This makes it simple to update the firmware of a field system, for example. In the field, the Cyclone unit may be powered by using a Cyclone_PowerPack, which is a lightweight and compact lithium ion battery.  The combination of the Cyclone programmer and the battery pack creates a fully operational field programming setup that is lightweight, compact, and extremely portable. 

All that is required for a field update is to connect the battery-powered, pre-programmed Cyclone to the target. Flash programming occurs directly from the Cyclone image to the target by a simple touch of the Start button. Once initiated, programming launches and the on-board LCD displays the current state of the programming process. The final result, which is displayed on the LCD screen and with highly visible LEDs, clearly indicates a successful programming result.

If you use the ELF/DWARF file format with P&E's Programming or Debugging software, download one of our free C development kits to view the information within the ELF/DWARF file.  Use Readelf to examine your application memory map, check your linker script, determine application size, view detailed debugging information, and more. 

We include the GNU Readelf utility with our C development kits, PKGPPCNEXUS for PowerPC 55xx and PKGCFZ_PRO for ColdFire.  These packages give you a complete set of development tools including the P&E ICD debugger, PROG Flash programming software, register viewing software, WinIDE editor, target specific project templates, and a GNU compiler toolchain. 

Download PKGPPCNEXUS Starter Edition

Download PKGCFZ_PRO Starter Edition

You can control Readelf and the entire compiler toolchain from WinIDE.  During compilation, you can automatically process the compiler output file with Readelf and dump the information to a text file.  Also, take advantage of Readelf with any target architecture - if you're not targeting ColdFire or PowerPC 55xx, you can install one of our free C development kits and use WinIDE as a stand-alone ELF/DWARF viewer.

FAQ 118:  How do I configure WinIDE to launch Readelf?


FAQ 91:  How do I use ICD to debug my C source code using the ELF/DWARF debug file format?


UPDATE: Learn more about the Readelf output here.


When it comes to production programming, a lot of times one or more serial numbers are required.

P&E has developed a utility called SERIALIZE, which allows the generation of a .SER serial number description file. This graphical utility sets up a serial number which will increment according to the parameters set by the user.

For P&E interactive programmers (PROGx software), the .SER files are stored on the PC and updated every time a serial number is programmed to the target.

For Cyclone stand-alone operations, a similar mechanism has been implemented, except that the serial number structure is stored in the Cyclone's non-volatile internal FLASH memory. The .SER file is used to obtain the initial serial number. Below we'll describe how a user can take advantage of this feature in stand alone operations.

Assuming that a user only needs one serial number for his product, the following sequence of operations can be specified when he creates the SAP image:

CM Corresponding programming algorithm for his product

SS Corresponding object file for his product





CS Corresponding .SER file for his product created using the Serialize utility


After storing the image on the Cyclone, a user can simply press the "START" button and watch the target be programmed with the serial number specified in the .SER file. Another press of the "START" button will program the target with the next serial number.

Multiple memory modules and multiple serial numbers can co-exist in one SAP image. The following are example scripts of two programming algorithms and three serial numbers:

CM Programming algorithm 1

SS Object file 1





CS .SER file 1


CM Programming algorithm 2

SS Object file 2





CS .SER file 2


CS .SER file 3


Once the SAP image is stored in a Cyclone, pressing the "START" button will automatically carry out all the operations listed above in sequence. Memory module 1 will contain the serial number specified in the first .SER file. Memory module 2 will contain the serial number specified in the second .SER file, and the serial number specified by the third .SER file. Another press of the "START" button will automatically program the next serial numbers in the target.

This serialize mechanism may even be used when a user wants to program some static data to different locations without using the "PB" or "PW" commands - the user can simply create a .SER file with all constants.

Please refer to this post for more information on the Serialization utility.


develP&E offers a set of In-Circuit Debuggers that are packed with powerful scripting features. Whether you are stepping through a couple of lines of assembly code or debugging a C-level source, P&E's toolset can help you get the job done. P&E's In-Circuit Debuggers are designed with repeatable test and debugging procedures in mind. Therefore, the user can completely automate software tests by creating a macro script and saving the outcome in a log file. As a result, the user can avoid hours of repeatedly setting up software and firmware tests.

Here's a small demonstration of how the built in macro commands can be used to create and perform a repeatable firmware test on a 9S08AW60 processor. We'll be working with a simple assembly loop that's designed to toggle Port A every 20 CPU cycles. Please note that while the example below will be based on ICDHCS08 debugger, the same set of macro commands is present in all P&E debuggers. For a complete set of built-in macro features, please refer to the ICD COMMANDS section in the corresponding ICDxx.hlp file.

Source under test:

RAMSTART equ $70


     mov #$ff,$01 ; ptadd
     mov #$ff,$00 ; ptad
     lda #$ff
     mov #$00,$00 ; 4 cycles
     mov #$ff,$00 ; 4 cycles
     jmp loop ; 4 cycles

The macro outlined below will load our loop_example.s19 and .map files. At the same time it will set the program counter, set the breakpoints, and initialize variables. As the code executes, it will also capture the contents of the desired registers as well as the contents of all on-screen windows. All information will in turn be stored in a log file for later comparison and analysis:

LF test_output.log  ; creates log file
HLOAD loop_example.s19  ; load an .s19 with a map file
PC Main  ; set program counter to point to the beginning of the
; code
VAR $00  ; add a variable to a variable window
VAR $01  ; add a variable to a variable window
GOTIL Loop  ; run through initialization part of the code to the loop
DUMP $00 $01  ; dump the contents of registers $00 to $01 into the log
; file
BR Loop  ; set a breakpoint at the beginning of the loop
GO ; run the code until it hits a breakpoint
SNAPSHOT ; captures the current data in all open windows and stores
; them in a log file.
LF ; close log file

To execute the above macro, enter “macro” in the command line (located on the bottom of the ICD status window). Browse to the location where your macro is saved and open the file. Please note that any built-in commands can also be executed individually. This gives the user the opportunity to perform a step-by-step test of the macro prior to starting the automated debugging procedure.

Boston , MA— P&E Microcomputer Systems continues its commitment to programming automation and efficiency by announcing the release of an Automated Control Software Development Kit (SDK) for the Cyclone family of products.

The SDK features a dynamic link library (DLL) and supporting documentation which allow the user to create custom software applications that directly control P&E’s Cyclone PRO and MAX units. It also enables users to control multiple Cyclones with a single PC, modify stored images, manage multiple images, and program non-sequential dynamic data such as serial numbers.

The Cyclone Automated Control SDK is available in Professional and Enterprise versions to suit both small and large production scales. A Basic version with limited features is available for download at no cost.

More information is available on the P&E website on this link.

Boston, MA - P&E Microcomputer Systems announces that it has extended the support of its PowerPC Nexus tools to include Freescale’s new MPC56XX devices. This set of in-circuit debuggers, FLASH programmers, and hardware debug interfaces now supports both MPC55xx and MPC56xx devices, offering a comprehensive solution for Freescale’s advanced automotive microprocessors.

Boston, MA - P&E Microcomputer Systems now offers a rechargeable Power Pack for use with the Cyclone PRO and Cyclone MAX stand-alone programmers. When powered by a lithium ion long-runtime battery, a Cyclone unit is the perfect solution for field firmware updates that require portable, stand-alone programming. The Cyclone and PowerPack are lightweight, compact, and extremely portable.

Boston, MA - P&E Microcomputer Systems’ Cyclone MAX is an extremely flexible tool designed for in-circuit flash programming, debugging, and testing of Freescale microcontrollers.  The Cyclone MAX’s architecture support has now been extended to include the PowerPC Nexus family (MPC55xx).  Architectures already supported include the ColdFire (MCF5xxx), PowerPC (MPC5xx/8xx), and ARM (MAC7xxx).

P&E has developed Linux-supported versions of many of our UNIT Library Interface Routines. For several years, P&E Microcomputer Systems has offered the UNIT SDK in order to allow users of P&E's hardware to create custom applications for testing and other designs. With the addition of Linux support for many of the UNIT products, P&E continues to expand the range of users who can take advantage of these powerful tools.

UNIT Library Interface Routines for Linux are available for:

  • HCS08
  • HC(S)12
  • 683xx
  • ColdFire
  • PowerPC
  • Power PC Nexus

For more information on UNIT software for Linux or Windows, please visit P&E's website.

Boston, Massachusetts - P&E has released a complete, powerful, and inexpensive C-level Windows-based development suite for Freescale PowerPC MPC55xx processors. The package includes P&E's in-circuit debugger, flash programmer, development environment, GCC C Compiler, assembler, register decoder, and USB-ML-PPCNEXUS hardware debug interface. The USB-ML-PPCNEXUS debug interface is a high speed USB 2.0 peripheral which connects to a standard Freescale MPC55xx debug connector and provides the ability to debug your target in real time.

P&E has also released a 64K-limited edition of the development suite which a available for download at no cost.

The development suite is currently available here : PowerPC MPC55xx C-Level Development Suite.

Boston, Massachusetts— P&E Microcomputer Systems announced the availability of two new USB Multilink interface cables. The first is the USB-ML-PPCNEXUS, a JTAG/BDM interface for Freescale MPC55xx devices. The second is the USB-ML-16/32, a BDM interface for Freescale 68HC16/683xx devices. Both new interfaces connect from the USB port of a Windows-based PC to the target. P&E offers these new USB Multilink interfaces individually, or packaged with software (debugger, programmer, IDE) as part of a development kit.

P&E Microcomputer Systems, Inc. is pleased to annouce the release of the Cyclone MAX automated programmer and debug interface. The Cyclone MAX programs PowerPC (MPC5xx/8xx), ColdFire (MCF5xxx) and ARM (MAC71xx) devices, and operates either as a stand-alone unit, or connected to a PC. Like P&E's popular Cyclone PRO, the MAX allows the user to communicate using either Serial, USB, or Ethernet ports. P&E expects to add functionality to the Cyclone MAX, including the possibilty of support for new architectures, expandable storage, and a new visual interface.

Boston, Massachusetts— P&E Microcomputer Systems continues to expand its offering of USB Multilink BDM Interfaces by proudly announcing the release of two new interfaces for the ColdFire and PowerPC families. The USB-ML-CF is a USB-port-to-target BDM interface for the ColdFire MCF52xx/53xx/54xx families of processors. P&E has also released the USB-ML-PPCBDM, which is a USB-port-to-target BDM interface for the 5xx/8xx families of PowerPC devices. Both new USB Multilink BDM interfaces feature:

  • USB interface from PC to Multilink for fast programming and debugging, with the ease and compatibility of the USB interface. Higher download rate is over 3x faster than P&E's parallel port cable. Wide target operating voltage of 1.80v-5.25v.

  • No separate power supply required - power is drawn from the USB interface (draws less than 1mA from the target)

As always, P&E is offering these powerful new tools at an affordable price. Please see the USB-ML-CF and USB-ML-PPCBDM product pages on P&E's website for more detail.P&E Microcomputer Systems, Inc., established in 1980 and located in Boston, MA, is an industry trendsetter in hardware and software development tools for Motorola / Freescale microcontrollers.

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