PEmicro’s GDB server can be installed directly into an Eclipse based IDE from an update site on PEmicro’s website. This adds the ability to debug via PEmicro’s Multilink, Cyclone, and OpenSDA hardware interfaces via the standard GDB debugger. Features include flash programming, breakpoints, watchpoints, trim, memory preservation, real-time variables, semi-hosting, and more. PEmicro periodically updates the plugins on its website with new device support, new features, and bug fixes.
The Cyclone FX has the capability to automatically select and launch a programming image based upon a scanned barcode. This can generate an error if more than one image corresponds to the barcode or no images correspond to the barcode. The CYCLONE FX includes a way to quickly gain insight into the issue. A log file is created every time the barcode scanner operates and it details the scanned barcode as well as the analysis process used to select the appropriate programming image.
Different targets require a different power schemes that depend on the design of the target board, target voltages, and even the device architecture. PEmicro has designed their CYCLONE and CYCLONE FX to optionally power a target before, during, and after programming. Power can be sourced at many voltage levels from the Cyclone itself or sourced by an external power supply and switched by the Cyclone.
The CYCLONE and CYCLONE FX programmers from PEmicro have large 4.3” touchscreens which allow the user to see the Cyclone’s current status, select programming images, configure settings, and more. However, sometimes the Cyclone may be either at a remote location or physically inaccessible. For example, Cyclone programmers are often mounted within enclosed test fixtures and sometimes even have the screens physically removed to save space. In any of these cases, the touchscreen can also be accessed remotely, via Ethernet and USB.
P&E has just released pipelined programming algorithms for a variety of Power Architecture devices. These new pipelined algorithms can be huge time-savers for those who program Power Architecture devices either in development or on their manufacturing lines, as they result in 50% to 100% faster programming times than when using non-pipelined algorithms. These significant programming performance improvements are available for the following Power Architecture device families:
Automatic selection and launch of a specific flash programming image based on a scanned barcode can improve the speed and accuracy of production programming, especially when there is a varied product mix being programmed. Barcode scanning improves accuracy by making the process of selecting a programming image fast, automatic, and less vulnerable to user error. P&E's CYCLONE FX programmers have the ability to use a barcode scanner, connected via the Cyclone's host USB port, to initiate programming. When a barcode is scanned, the Cyclone selects a specific programming image based on the barcode and programs the target board accordingly.
BOSTON - December 14, 2016 - P&E Microcomputer Systems, Inc. has announced the release of support for macOS in P&E’s Eclipse GDB Server. P&E offers a downloadable GDB server plug-in for Eclipse-based 3rd party IDE’s including those by NXP, Atollic, and Somnium. It also features full support for P&E's Multilink debug probes and Cyclone production programmers, plus NXP’s openSDA series of debuggers and programmers. Apple® users are now able to take advantage of P&E's versatile hardware solutions using NXP’s software tools and P&E’s GDB server in their preferred operating system.
"macOS" is a trademark and "Apple" is a registered trademark of Apple, Inc. "ARM" and "Cortex" are registered trademarks of ARM Limited or its subsidiaries.
P&E Microcomputer Systems, Inc. has announced the release of a new Multilink development tool and a new Cyclone manufacturing tool, both focused specfically on ARM Cortex devices.
The development tool is the Multilink ACP, which joins P&E's successful line of Multilink debug probes. The Multilink ACP features support for ARM Cortex devices only, which allows P&E to offer this new Multilink at a terrific value.The Multilink ACP supports a wide variety of ARM device manufacturers. A full list can be browsed at P&E's ARM device portal.
Cyclone ACP FX
The manufacturing tool is P&E's new Cyclone ACP FX production programmer. The Cyclone ACP FX is a flagship Cyclone FX programmer, but with a focus on ARM devices only. The Cyclone ACP FX features blazing programming speed, a huge internal memory,enhanced security features (such as the ability to add restrictions to specific programming images),
an SD port for expandable memory, and expansion ports that enable unique, valuable plug-ins such as a bar code scanner for programming.
P&E will be showing these new tools for ARM device development and production, along with other new P&E technology, at ARM Techcon in Santa Clara, CA on Oct. 25-27. P&E welcomes visitors and will be at booth #801.
BOSTON - October 17, 2016 - P&E Microcomputer Systems, Inc. has announced the addition of support for Renesas' RH850 devices to P&E's diverse line of embedded systems tools.
Renesas' RH850 is a family of high-performance, low power automotive microcontrollers. P&E's powerful Cyclone for Renesas stand-alone programmer now supports these and many other families of Renesas devices.
Current users of compatible P&E products can update their product firmware to add support for these devices. The corresponding programming algorithms can be downloaded from P&E's online support center.
BOSTON - June 16, 2016 - P&E Microcomputer Systems, Inc. today announced the ability to add usage restrictions to programming images created for the Cyclone FX stand alone programmer. These usage restrictions include the ability to limit programming to a specific date range and also to set a maximum number of programming operations which can occur. The effect of this is that the user can limit the duration and amount of programming allowed by an image. This can be useful for protecting the IP contained within a programming image as well as making sure that programming images in production are not too far out of date. These restrictions persist even when the images are deleted/restored on a Cyclone unit's internal memory or SD card. Images are encoded in such a way as to deter tampering.
Image restrictions are set in the Cyclone Configuration Utility
The Cyclone FX programmer is a stand-alone in-circuit programmer which supports many NXP and ARM Cortex based devices. Cyclone FX owners who wish to update their Cyclones can download the latest software and firmware from P&E's website.
Programming count displayed on the Cyclone FX home screen
The Automated Control Package features a Windows dynamic link library (DLL), command-line script application, and supporting documentation making it simple to create custom software applications that directly control Cyclone units. It also enables users to control multiple Cyclones with a single PC, modify stored images, manage multiple images, and program non-sequential dynamic data such as serial numbers. Example projects are provided in several popular development languages.
The Cyclone Automated Control Package is available in Professional and Enterprise versions to suit both small and large production scales. The Enterprise edition includes documentation describing the RS-232 and Ethernet protocols. A Basic version is available for no cost.
BOSTON – March 28, 2016 - P&E Microcomputer Systems is now shipping Rev. C of the Cyclone for ARM devices, which represents an evolution in both features and value from the older Rev. B model. P&E's Cyclones have set the standard for powerful, versatile production programming and debug. The Cyclone for ARM devices was designed to offer the very best of the Cyclone platform with a focus on enhanced security, extremely fast performance, test, and expandability.
Rev. C of the Cyclone for ARM devices supports ARM® Cortex® devices from many different manufacturers - click the graphic on the right for a full list of supported devices. An easy-to-use access panel opens to reveal JTAG/SWD headers. This new Rev. C Cyclone represents an even more outstanding value than its predecessor, given its rich feature set and affordable cost.
BOSTON – March 15, 2016 - P&E Microcomputer Systems is now shipping the Cyclone Universal FX, which is the flagship model of P&E's next-generation Cyclone programmers. P&E's Cyclones have set the standard for powerful, versatile production programming and debug. The Cyclone Universal FX was designed to offer the very best of the Cyclone platform with a focus on enhanced security, extremely fast performance, test, and expandability.
The Cyclone Universal FX combines support for many NXP 8-/16-/32-bit architectures with support for ARM® Cortex® devices from many different manufacturers. P&E has maintained compatibility with their existing product line while combining support for all of these target architectures into a single unit.
Cyclone Universal FX Features:
(Features in bold are key differentiators between the Cyclone Universal and Cyclone Universal FX
BOSTON – February 4, 2016 - P&E is pleased to announce that support has been added to its products for files using version 3 and version 4 of the ELF/DWARF format. This is in addition to existing support for ELF/DWARF version 2 and includes both debug and object information handling. Support for 64-bit objects and structures within the ELF/DWARF files has also been added.
Support for these additional file formats is available today in P&E's debug, flash programming, and test products.
BOSTON – November 13, 2015 - P&E Microcomputer Systems is now shipping the Cyclone Universal, which is the first of P&E's next-generation Cyclone programmers. P&E's Cyclones have set the standard for powerful, versatile production programming and debug. The Cyclone Universal was designed as the first in a next-generation Cyclone platform with a focus on security, performance, test, and expandability.
The Cyclone Universal combines support for many NXP/Freescale 8-/16-/32-bit architectures with support for ARM® Cortex® devices from many different manufacturers. P&E has maintained compatibility with their existing product line while combining support for all of these target architectures into a single unit.
BOSTON – October 12, 2015 - P&E Microcomputer Systems has further expanded its ARM® device support by today announcing support for Maxim MAX716xx processors. Users of P&E's Cyclone for ARM devices production programmer will be able to take advantage of this support to work with these Maxim ARM devices.
More about these devices, from Maxim's product page: "The MAX71617 is a low-power, single-phase energy measurement system-on-chip (SoC), and the MAX71637 is a low-power polyphase energy measurement SoC."
Users may visit pemicro.com/arm to check whether their specifc device is supported.
ARM and Cortex are registered trademarks of ARM Limited or its subsidiaries.
BOSTON – July 21, 2015 - P&E Microcomputer Systems has further expanded its ARM® device support by today announcing support for Cypress' PSoC® 4 and Toshiba's TX00/TX03/TX04 processors. Users of P&E's Cyclone for ARM devices production programmer will be able to take advantage of this support to work with these Cypress and Toshiba ARM devices.
Cypress' PSoC® 4 are very low-power 32-bit ARM Cortex®-M0 devices that can integrate analog and digital ICs. Toshiba's TX00, TX03, and TX04 represent a selection of ARM® Cortex®-M devices that, collectively, offer high energy efficiency, high-precision analog functions, high code density, fast interrupt response times, and DSP extensions.
Users may visit pemicro.com/arm to check whether their specifc device is supported.
ARM and Cortex are registered trademarks of ARM Limited or its subsidiaries. PSoC is a registered trademark of Cypress Semiconductor Corporation.
BOSTON, MA – July 14, 2015 - Following their debut at the 2015 Freescale Technology Forum, P&E's soon-to-be-released Cyclone Universal and Cyclone Universal FX are now available to pre-order. Production quantitites of both new Cyclone programmers are expected to ship by Sept. 15 (subject to change). Those interested in placing a pre-order or simply reviewing the features of our next-generation production programming, test, and debug interfaces may do so at the Cyclones' P&E product page. These new Cyclones each support many architectures and offer impressive feature sets that may include:
Large internal memory: 1GB+ secure memory storage.
Focus on security: Internal memory protection & encryption, anti-tampering technology, tie images to specific Cyclones, programming count limits, date range limits, logging, etc.
AUSTIN, TX – June 22, 2015 - P&E's Cyclones have set the standard for powerful, versatile production programming and debug. We have completely redesigned the Cyclone Platform with state of the art, high-speed technology. We have maintained compatibility with our existing product line while combining support for many target architectures in a single unit and focusing on outstanding security, performance, and features.
Join us at the Freescale® Technology Forum (FTF) in Austin, June 22-25. Come visit us at booth #617 for a chance to win one of two Cyclone Universal FX units, once they are released!
In addition to supporting more target architectures, these new Cyclones offer several improvements over their predecessors:
Large internal memory: 1GB+ secure memory storage.
Focus on security: Internal memory protection & encryption, anti-tampering technology, tie images to specific Cyclones, programming count limits, date range limits, logging, etc.
BOSTON – June 3, 2015 - P&E Microcomputer Systems is now providing serial SPI memory device programming algorithms for devices attached to ARM® Cortex-M microcontrollers. There are many reasons to use P&E’s algorithms for your programming requirements. Some of the more significant reasons are:
These algorithms work on all current manufacturers’ Cortex-M0…M4 microcontrollers.
Program both your microcontroller memory and attached SPI memories in one simple step.
Any four I/O port pins can be used to talk to the SPI devices: CLK, CS, MOSI, and MISO.
Any combination of microcontroller port pins can be used to connect to SPI memory devices.
Very fast bit banging software is used to implement these efficient and universal algorithms.
Data transfer rate to the SPI is increased by faster microcontroller operating frequencies.
Rates of over 600 kilobytes per second have been observed on a 120 MHz microcontroller.
All P&E SPI service algorithms automatically do a verify during the programming process.
No need to fight with complex SPI hardware during development and production processes.
Even if you use SPI hardware in your design, P&E’s algorithms can still be effectively used.
Configuration for your hardware setup is easy and readily updated during development.
Algorithms work seamlessly with P&E’s Cyclone mass production hardware and software.
Usable with P&E’s well-known GUI and Command Line programming software products.
Compatible with P&E’s SWD/JTAG development hardware interfaces such as Multilinks, etc.
Over 1100 SPI memory devices are currently supported and the list is always increasing.
Algorithms exist for Flash, EEPROM, FRAM, MRAM, RAM, nvRAM, and other device types.
Example microcontroller setups provided for: Freescale, TI, Toshiba, NXP, ST, and Spansion.
The SPI programming algorithms are divided into two separate archives, one for NXP LPC ARM devices and one for the other P&E-supported manufacturers (Freescale, STMicroelectronics, TI, etc.). This is because NXP LPC devices have RAM at address 10000000, whereas the rest have RAM at address 20000000. The archives may be downloaded at P&E's support center page for SPI algorithms.
For further information on this product, to peruse the manual with various setup examples, see a list of current algorithms, or request new algorithms, please view P&E's flash programming algorithm page in the Support Center.
BOSTON – September 9, 2014 - P&E Microcomputer Systems has developed a new pipelined version of its flash programming engine for Kinetis and other ARM® Cortex™ devices with more than 4KB of RAM by leveraging some unique aspects of the architecture. This pipelining mechanism improves already fast programming rates by up to 50%.
Support has been released for most Kinetis devices with other device support to follow. The pipelined algorithms are available for use with the latest software/firmware versions of: Cyclone MAX, Cyclone for ARM devices, PROGACMP, Freescale's CodeWarrior and Kinetis Design Studio, and P&E's GDB Server.
Cyclone users will need the latest version of the software for their Cyclone to use the pipelined algorithms. The latest Cyclone MAX software is available to download from P&E's support center. The latest Cyclone for ARM devices software will be made available shortly. Contact P&E to update to the latest version of PROGACMP.
ARM is a registered trademark and Cortex is a trademark of ARM Limited.
BOSTON – August 28, 2014 - P&E Microcomputer Systems announced the addition of support for Freescale's high-performance S12Z devices to its popular Cyclone PRO stand-alone/automated in-circuit programmer. Freescale's S12Z devices include the S12ZVC, S12ZVH, S12ZVL and S12ZVM families. This further expands the range of Freescale architectures that the Cyclone PRO is able to program, which includes HC(S)12(X), RS08, HCS08, HC08 and ColdFire+/V1 devices.
BOSTON – August 27, 2014 - P&E Microcomputer Systems announced the addition of support for Freescale's MPC5xx/8xx devices devices to its high-speed Multilink Universal FX development interface. This addition enhances the all-in-one capabilities of the Multilink Universal FX - P&E's flagship Multilink interface - and solidifies P&E's future support for Freescale's MPC5xx/8xx architecture.
BOSTON – September 25, 2013 - P&E Microcomputer Systems announced support for a group of Renesas' RX family of devices in Rev. C of the Cyclone for Renesas®In-Circuit Flash Programmer. P&E has implemented support for Renesas' RX600 devices and will continue to add support for other RX devices in the near future. RX is a range of 32-bit Renesas microcontrollers that feature high performance and code efficiency while also offering low power consumption and new/enhanced peripherals. The latest version of P&E's Cyclone for Renesas adds RX to existing support for RL78,R8C, M16C and M16C/80, M32C, H8 and H8S/Tinydevices.
Renesas is a registered trademark of Renesas Electronics Corporation.
BOSTON – September 12, 2013 - P&E Microcomputer Systems announced the release of its PROGS12ZZ in-circuit flash programming software for Freescale's S12Z devices. S12Z MCUs are integrated, mixed-signal devices designed for efficiently developing automotive applications. PROGS12ZZ works in tandem with P&E hardware interfaces, such as the Multilink Universal, Multilink Universal FX, or Cyclone PRO, to program Freescale S12Z devices. These pairings represent a variety of economical, versatile, and powerful programming solutions.
BOSTON – August 2, 2013 - P&E Microcomputer Systems announced the release of Rev. C of its Cyclone for Renesas® In-Circuit Flash Programmer, which adds support for Renesas' RL78 devices. RL78 is a new family of Renesas microcontrollers that are compact, low-cost, and designed for extremely low power applications. Renesas offers RL78 devices that are tailored towards general purpose, lighting, automotive, and other applications. The latest version of P&E's Cyclone for Renesas adds RL78 to existing support for R8C, M16C and M16C/80, M32C, H8 and H8S/Tiny devices, and opens the path for future support of additional devices such as the RX family.
Renesas is a registered trademark of Renesas Electronics Corporation.
BOSTON – July 2, 2013 - P&E Microcomputer Systems has released its new PROGDSC flash programming software. PROGDSC is Windows-based in-circuit flash programming software for Freescale's DSC devices, and includes the CPROGDSC command-line programmer for scripted automated programming. Those who wish to use the software may download the full version from a link on the product page, where they will also find a link for requesting a license for the software free of charge.
PROGDSC communicates with target devices through one of P&E's compatible hardware interfaces. The Multilink Universal and high-speed Multilink Universal FX are development interfaces, while the Cyclone MAX is one of P&E's flagship Cyclone stand-alone production programmers: it's made to withstand the rigors of a production environment, can be used manually or fully automated, and is the ideal solution when programming speed is crucial.
BOSTON – Mar. 15, 2012 - P&E Microcomputer Systems Inc., a leading developer of third-party tools for Freescale microcontrollers, has announced the addition of support for Freescale DSCs (digital-signal controllers) to key P&E development and production programming interfaces. Freescale DSCs are designed to blend processing power with specific, optimized control loop capabilities. P&E's DSC-compatible products represent a range of feature sets and price points in order to accommodate projects of any scope and budget.
P&E's Cyclone MAX, a flagship Automated Programmer and Debug Interface that is designed to handle a variety of tasks, including low and high volume programming in demanding production environments, now offers support for the following Freescale DSC families: MC56F80xx, 56F82xx, MC56F83xx, and MC56F84xxx. In addition, the new Cyclone MAX firmware (v.7.70) streamlines the unit's LCD display and provides more user selected and customized information.
The USB Multilink Universal and the high-speed USB Multilink Universal FX also support Freescale's MC56F80xx, 56F82xx, MC56F83xx, and MC56F84xxx DSC families as part of an "all-in-one" approach that includes support for many other Freescale MCU architectures. The USB Multilink Universal is P&E's entry-level all-in-one development interface, and the USB Multilink Universal FX features up to 10x faster download speed and the ability to supply target power, while remaining an excellent overall value.
All three of these DSC-compatible interfaces are natively supported by Freescale's Codewarrior 10.2. More information on the Cyclone MAX, USB Multilink Universal, USB Multilink Universal FX, and compatible software is available at www.pemicro.com.
BOSTON – Feb. 28th, 2012 - P&E Microcomputer Systems Inc., an industry trendsetter in hardware and software development tools for Freescale microcontrollers, is introducing a series of hardware and software development tools that support Freescale’s new S12ZVM device family. This support includes a sub-$1000 trace interface, low-cost development interfaces, debug and programming software, and production programming equipment.
P&E’s TraceLink is the first trace product on the market that allows developers to capture real-time external trace information from Freescale’s S12ZVM device family. Developers facing ever-increasing speed and complexity will benefit significantly from the insight that this feature provides into the real-time execution of their code. “The TraceLink brings the highest level of debug capability to Freescale’s new S12ZVM device family while maintaining an affordable, sub-$1000 price point” says Edison Tam, chief architect of the TraceLink product. “With a huge amount of on-board memory, the TraceLink can continuously record processor events without having to stop or disturb the running application which is extremely important to our customers.”
“We are excited to work closely with P&E Microcomputer Systems on the new TraceLink development tool. This product allows developers to capture real-time external trace information from the S12ZVM device as it runs.” Said Steve Pancoast, vice president of Freescale’s Automotive, Industrial & Multi-market Product Solutions group. “Given the large amount of trace storage, the TraceLink can continuously record processor events without having to stop or disturb the running application, which is extremely important to many of our customers. Equally significant, this industry-turning product will be available at competitive pricing.”
The S12ZVM family of devices is also supported by the Multilink Universal and Multilink Universal FX development interfaces, and by the Cyclone PRO flash-programming interface offered by P&E Microcomputer Systems. The Multilink Universal and Multilink Universal FX are ideal for design and development, while the advanced production features of the Cyclone PRO is irreplaceable in a fast-paced manufacturing environment. The Cyclone is designed to provide the highest level of flexibility, and features an on-board LCD, Ethernet/USB/Serial interface support, and internal memory capable of storing multiple FLASH images for different manufacturing applications.
P&E Microcomputer Systems, Inc.
(617) 923-0053 xt 713
keith.mcneil (at) pemicro.com
P&E continues to expand on its line of all-in-one interfaces with the launch of the high-speed USB Multilink Universal FX. Like P&E's original all-in-one interface, the USB Multilink Universal, the new USB Multilink Universal FX supports a varirety of Freescale MCUs, including: Kinetis, Qorivva 55xx/56xx, ColdFire V1/ColdFire+ V1, ColdFire V2-4, HC(S)12(X), HCS08, RS08, Power Architecture PX Series, and DSC. However the new FX interface can download at speeds up to 10x faster and can provide power to the target processor, among other enhancements.
The new USB Multilink Universal FX is natively supported by recent versions of CodeWarrior®, current P&E software applications, and toolchains from many Freescale partners including Keil and Cosmic.
More information about the USB Multilink Universal FX is available on the product page at P&E's website.
presented its new USB Multilink Universal, an ALL-IN-ONE development interface, at the recent Freescale Momentum conference. The revolutionary ALL-IN-ONE interface concept
was very well received by conference attendees. USB Multilink Universal is a single interface that supports Freescale’s HCS08, RS08, HC(S)12(X), Coldfire V1/+V1/V2-V4, Qorivva
MPC55xx/56xx, and Kinetis ARM microcontrollers. Thus, it eliminates the need to
purchase different hardware interfaces to support specific devices that belong to those MCU families.
P&E also previewed two upcoming products: the USB Multilink
Universal FX and Tracelink. The USB Multilink Universal FX is an enhanced, very
high-speed version of the USB Multilink Universal. The Tracelink interface will support
trace capture for 32 bit Freescale device architectures.
P&E has released its groundbreaking new USB Multilink Universal all-in-one interface. The USB Multilink Universal is an economical, reliable USB-to-target interface that uses multiple headers to support Freescale's HCS08, RS08, HC(S)12(X), ColdFire V1/+V1 & V2-4, Qorivva MPC55xx/56xx, and Kinetis ARM microcontrollers. The USB Multilink Universal includes multiple ribbon cables to allow connections to the various supported devices. The USB Multilink Universal's case simply flips open for easy access to the headers.
It is supported by P&E software, in addition to Freescale's Codewarrior and software from other third party vendors. A configuration utility is available on P&E's website which allows configuration of the USB Multilink Universal for use with older software packages.
P&E is also developing the USB Multilink Universal FX, an enhanced, high-speed version of the USB Multilink Universal interface.
This video provides a brief comparison of the features of two popular P&E hardware interfaces, the USB BDM Multilink and the Cyclone PRO. This overview is intended to help users determine which interface is best suited for their project. More information about each interface can be found on the USB-ML-12 and Cyclone PRO product pages.
P&E is pleased to announce that 64-bit Windows support has arrived, including support for Windows 7. P&E software has been upgraded to work under Windows 7 (and other Windows 64-bit operating systems) by using the latest version of our drivers - P&E Hardware Interface Drivers 10. There is no need to worry about P&E software compatibility if you're migrating to a Windows 64-bit OS at home or in the office.
P&E is committed to ensuring a smooth transition to these newer operating sytems for our customers. Customers who have purchased P&E software within the last 12 months can contact us for a free ugprade. Customers who have purchased software between 12 and 24 months ago are eligible to upgrade by purchasing the latest version of the software at a 50% discount from the full price.
Unfortunately, due to OS and hardware driver limitations, P&E legacy products such as USB-ML-12 Rev. A, USB-ML-CF Rev A, the BDM Lightning Card and also parallel port versions of our programmers are not supported under Windows 7 and 64-bit systems. However, we are committed to supporting these products under 32-bit operating systems such as Windows 98/2000/XP/Vista by continuing to offer Version 9 of our P&E Hardware Interface Drivers. These can be downloaded from the Documentation and Downloads section of P&E's website, or directly at the following link:
We're pleased to announce the release of our latest device drivers. This update includes support for Microsoft Windows XP, Vista, and Windows 7 Operating Systems for both 32-bit and 64-bit architectures, as well as some minor bug fixes.
Run the file drivers_10_install.exe. If you have an older version of our drivers installed, the setup will automatically perform the update.
NOTE: The latest drivers no longer include support for Windows 98 and ME, but P&E will continue to make our older drivers available. Support for PCI devices (e.g., BDM Lightning) and Parallel port devices has been removed for Windows Vista and later, as well as all 64-bit operating systems.
P&E drivers allow P&E applications to communicate with P&E hardware via the parallel port, PCI bus, Ethernet, Serial, and USB.
P&E Launches Cyclone Programmer For Renesas Devices
The power of P&E's Cyclone programmers is now available for Renesas! P&E's Cyclone for Renesas is a flexible, affordable in-circuit flash programming solution for Renesas devices that excels in a demanding production environment. After configuration, operation is as simple as one touch.
Support is currently available for the R8C, M16C, and H8 families. A complete listing of supported devices is available here. Please contact us for information about support for other devices.
The Cyclone for Renesas includes an extremely useful LCD Menu Display that greatly enhances the Cyclone's stand-alone capabilities. The LCD Menu Display allows the user to:
Configure the Cyclone without a PC
Quickly view and select from multiple programming images
Easily perform programming operations in stand-alone mode
Get direct feedback about programming results
No need to swap programming images! The internal memory of the Cyclone for Renesas manages multiple images. Load several different programming images onto the Cyclone and choose between them using either the PC software or the LCD Menu on the unit itself. The Cyclone's memory can also be expanded with optional CompactFlash activation.
Automation can yield a big increase in productivity. P&E includes software with the Cyclone for Renesas that allows the user to automate control of a single Cyclone via a command-line executable or a .dll.
NOW AVAILABLE - P&E has introduced the Cyclone Automated Control Package, which allows users to manage multiple Cyclones simultaneously. Any supported devices can be programmed in parallel, even if they are different devices with different data.
Please visit P&E's website for information on the Cyclone Automated Control Package (available separately).
Expand the memory of your Cyclone for Renesas with P&E's new Compact Flash support. Store more images and larger images while adding flexibility and efficiency by reducing your need to be connected to the PC.
This video gives a demonstration of how to load a programming image onto a
CompactFlash card in the expansion port of P&E's Cyclone products.
CompactFlash activation is a powerful feature that lets users expand
the memory and versatility of their Cyclone:
P&E’s Cyclone PRO/MAX Stand Alone Programmers offer an impressive array of capabilities such as in-circuit flash programming, stand-alone programming, and as much as 7MB internal non-volatile memory for storing programming images. And now this memory space can be expanded via optional software which enables the Cyclones’ CompactFlash interface. The expanded storage feature simplifies management of Stand-Alone Programming images. This Expert’s Corner explains how to take advantage of the CompactFlash card feature to facilitate the Stand-Alone Programming process.
One of the key features of the Cyclone PRO/MAX Stand-Alone Programmers is the ability to store all necessary programming information - binary data, algorithm information, and programming settings – in the Cyclone’s internal memory, in a format known as the Stand-Alone Programming (SAP) Image. This allows programming operations to be initiated by pushing a single button.
There are currently two methods that can be used to load a SAP image onto a Cyclone. If only a single image is necessary for production, that image can be stored directly on the Cyclone using the “Cyclone Image Creation Utility”.If several images are necessary for production, the “Cyclone Image Creation Utility” can first be used to create all the SAP images, and then the “Cyclone Image Manager” can be used to load all the images simultaneously into the cyclone.
These methods are useful for updating small SAP images stored internally, or when the unit is easily accessible from a host PC. However, the procedure becomes a bit more involved if the Cyclone unit is not easily accessible. If the unit is at a different manufacturing plant, for example, or overseas, the user would have to obtain the Cyclone, update the images, and then send it back to its original location. However, with the addition of CompactFlash support this process becomes a matter of simply removing a CompactFlash card with one set of images and plugging in another with the new set, thereby reducing the need for an additional PC and engineering support. This makes it very easy to reconfigure images in the field.
In addition, activation of the Cyclone’s CompactFlash capability provides support for images which are larger than the internal memory storage space. A firmware image of 16 MB intended for programming into a hybrid engine controller, for example, can now easily be stored on a CompactFlash card.
The following sections demonstrate how to use the CompactFlash feature. We will create a SAP image example and then store it on a CompactFlash card in a Cyclone MAX, Rev. B.
First we create a SAP image using the “Cyclone Image Creation Utility” and save the SAP image on the PC.Then we transfer the image onto the Cyclone’s CompactFlash card. In the screenshot below, the “Cyclone Image Creation Utility” is configured for Freescale Power Architecture 5534 with a typical programming sequence:
Additional settings for the SAP image may need to be configured depending on the architecture. For the Power Architecture there are three other settings to configure, which are as follows:
1. BDM Shift Frequency: 5, which corresponds to a communication frequency of 2.2 MHz. This clock cannot typically exceed a 1/6th of the processor bus frequency. 2. Reset Delay: 0. The reset delay section allows the user to set a delay before attempting communication. It is generally used if a reset driver exists on the target board which further asserts reset for a longer delay. In this example we will use a reset delay of zero. 3. Image Description: Field_Upgrade_Hybrid_3.49. The field for “Image Description” is used for naming each image that is created.
After verifying that the programming settings are correct, use the “Store Image to Disk” button to save the image on the PC. Then load the image into the CompactFlash card by using the “Cyclone Image Manager Utility”.
In this example, the SAP image is saved on the Desktop:
3. Using CompactFlash – Inserting a CompactFlash Card
Insert the CompactFlash card into the “Flash Expansion Port” on the Cyclone Max Rev. B. It is not necessary to power off the Cyclone Max Rev. B before inserting the CompactFlash Card.
Upon insertion of a blank CompactFlash card the Cyclone prompts the user to format the card for use with the Cyclone device. The user should use only a P&E branded CompactFlash card to guarantee proper operation.
4. Using CompactFlash – Storing an Image into CompactFlash
If the Cyclone’s CompactFlash capabilities have been activated, the “Cyclone Image Manager” will display a section that can be used to manage images stored on the CompactFlash. The new Cyclone Image Manager software is sold separately and must be registered before use. Below is a screenshot which shows the “Browse & Add Images to CompactFlash” section activated:
In this example, the Cyclone MAX, Rev. B is named “Persepolis” and has an IP address of “126.96.36.199” with two SAP images already stored in its internal memory.
The section labeled “Browse & Add Images to Internal Memory” has been updated so that SAP images stored in internal memory will be displayed with a prefix of “IN#:” The prefixes are automatically added after a SAP image is stored. The functionality of the buttons, “Remove All”, “Remove”, and “Add”, remain the same as before. “Remove All” will remove all the images from the internal memory. “Remove” and “Add” are used to configure a list of images to be stored in the Cyclone MAX, Rev. B internal memory. A screenshot of this section appears below:
To store a SAP image on the CompactFlash, click on the “Add” button
under the second section, “Browse & Add Images to CompactFlash”.
In this example, the SAP image “Field_Upgrade_Hybrid_349.SAP” created in Section 2 is selected. After selecting the correct SAP image, click open. The SAP image should now be listed in the “Browse & Add Images to CompactFlash” section. Shown below is a screenshot of “Browse & Add Images to CompactFlash” before committing changes. The prefix “EX#” is added before the file name to designate it as CompactFlash external memory.
After verifying that the correct SAP image has been added to the list, click on “Commit Changes” to store the image into the CompactFlash card. Shown below is a screenshot of “Browse & Add Images to CompactFlash” after committing changes. Note that the image is now listed on the left.
Several SAP images can also be added at the same time. In the screenshot below, two extra SAP Images have been added to the CompactFlash card.
Now that the SAP images have been added to the Cyclone’s CompactFlash card, we can use LCD screen and interface buttons on the Cyclone MAX, Rev. B to select which image to use for stand-alone programming. The next section discusses the steps needed for selecting a SAP image.
If you wish you may watch this brief video demonstrating how to load a programming image onto the CompactFlash.
5. Using CompactFlash – Selecting an Image on the LCD screen
After storing the SAP images into the internal memory and CompactFlash, the status window displayed on the Cyclone MAX, Rev. B appears as below:
To change the selected SAP image press the “Menu/Select” button, which brings up the main menu:
Then press the “Menu/Select” button again when “Select SAP Image” is highlighted.
This will bring up a list of available SAP images. As mentioned previously, the prefix “IN#:” indicates that an Image is stored in internal memory and the prefix “EX#:” identifies that an Image that is stored in CompactFlash. Scroll until the desired image is highlighted and then press “Select”.
Once the SAP image is selected, its name will be displayed in the status window:
For added data security, information can only be written to the CompactFlash through the Cyclone MAX, Rev. B and Cyclone PRO, Rev. C, and datasets cannot be extracted from the CompactFlash once they have been written.
With the new CompactFlash card feature, P&E’s Cyclone PRO and Cyclone MAX Stand-Alone Programmers are no longer constrained by a limit of eight SAP images in the internal memory. Furthermore, updating a SAP image at an off-site production facility or on the field is now as easy as sending a CompactFlash with the new SAP Image. Archiving each new version of an image becomes easier by storing each new image on a separate CompactFlash Card.
P&E engineer Edison Tam demonstrates how to program
Freescale's QE128 with P&E's Cyclone PRO stand-alone automated
programmer, and gives an overview of the development and production
capabilities of the Cyclone PRO. To learn more, please visit the Cyclone PRO product page:
P&E's flash programming software PROG12Z now supports the Freescale MC9S12XE family of microcontrollers.
The MC9S12XE family of microcontrollers comes with unique flash
memory called D-Flash that can be allocated for Emulated EEPROM (EEE)
which mimics the small sector size and endurance of real eeprom. Before
you can program the D-Flash or EEE, the D-Flash must be configured with
the "Full Partition" command PROG12Z. This article discusses
how to program the D-Flash of MC9S12XE100 using PROG12Z. The P-Flash does not support the allocation of EEE and therefore does not require partitioning.
The size of the D-Flash on the MC9S12XE can be up to 32KB or 128
sectors of 256 bytes each. You can allocate up to 4KB or 16 pages of
256 bytes each to be used for EEE. Please see Freescale application
note AN3490 for a more detailed overview of the EEE implementation.
There are two parameters that control how the software
configures the memory: DFPART and ERPART.
DFPART = Number of D-Flash sectors reserved as User D-flash (128 total)
ERPART = Number of pages reserved for EEE (16 total)
The two parameters are required to meet two size conditions to be valid:
1. (128-DFPART) / ERPART >= 8
2. (128-DFPART) >= 12 if ERPART==1
The following table shows how the flash memory can be allocated
towards D-Flash and EEE. The arrows indicate that any number in that
range is a valid amount of sectors for D-Flash. DFPART and ERPART are
in hexadecimal notation.
Open Prog12z and connect to the target board. After entering
background mode, the software will prompt you for an
algorithm. There are two seperate algorithms for D-Flash and EEE. The
D-Flash algorithm is
EEE algorithm is "Freescale_9S12XEP100_1x16xmax2k_max4K_EEPROM_linear_1k_page.12P".
Lets choose the algorithm for D-Flash. After selecting your S19 file and before programming, execute the Full
Partition (FP) command. The software will prompt you to enter a value in hexadecimal that is the combination of DFPART and ERPART parameters.
"8000" - Enables 128 sectors (32 KB) of D-Flash and 0 pages of EEE
"200C" - Enables 32 sectors (8 KB) of D-Flash and 12 pages (3 KB) of EEE
"100C" - Enables 16 sectors (4 KB) of D-Flash and 12 pages (3 KB) of EEE
"0010" - Enables 0 sectors of D-Flash and 16 pages (4 KB) of EEE
When you want to program the EEE, you should choose the algorithm for EEE. You do not need to run the Full Partition command again unless you want to change the memory configuration. Note that setting up the memory configuration using the FP
command will erase all the contents of both D-Flash and EEE. If you
get the error message "Started. Error during .12P specified function.",
you have entered an invalid value.
The D-Flash begins at 0x100000. If all your memory is allocated towards D-Flash only, execute the Upload Module (UM) command to dump the memory to a S19 file. UM reads the entire flash regardless of how it was partitioned. If there is D-Flash and EEE, execute the Upload Range (UR) command instead. For example, if there is 8 KB of D-Flash, then upload the range 0x100000 to 0x101FFF.
Systems that use memory-mapped external flash require special considerations from a programming perspective. Because there are so many variables, questions about external flash are among the most common types of technical support inquiries that we receive. In this article, we provide an overview of how the P&E PROG software handles external flash and offer some tips to help debug a system. The examples in this article relate to Freescale ColdFire devices, but the concepts can be applied to most microprocessor systems.
Hardware connections The following is the minimum set of signals required to access a memory-mapped external flash:
A[X:0] – Address signals D[Y:0] – Data signals CS – Chip Select WE or R/W – Write Enable OE – Output Enable
How PROG works P&E’s PROG software forces the processor into background (or "debug") mode, where it gains full access to the processor’s resources. The flash programming algorithm is then loaded into the processor’s RAM. The algorithm contains all of the routines necessary to erase and program the external flash.
PROG always moves the external flash so that it begins at address 0 for programming. If your own memory map is different, PROG will need to account for this with the correct base address.
Accessing the external flash The PROG software uses the processor to access the external flash. This means that from the processor’s perspective, it must be able to read and write to the external flash. Usually, this is all handled by the processor’s external bus interface. Most of the external flash algorithms provided by P&E assume that this configuration is already handled by the user.
For example, most processors automatically start up with CS0 as the global chip select. The processor uses this chip select for all external memory accesses until it is reconfigured by the user. Likewise, the processor checks certain signals during bootup to determine the width of the data bus on CS0.
Extra initialization Depending on the processor and external flash used, there may be some extra initialization that is not automatically performed by the processor on bootup, but is necessary before flash programming can take place. Users may perform this extra initialization by adding commands to the beginning of the algorithm itself. The algorithms may be edited with a simple text editor such as Notepad. Refer to the PROG help file for more detailed information on these commands.
1) Processor’s internal SRAM needs to be enabled, because it is disabled at bootup NO_ON_CHIP_RAM CONTROL=80000001/0C05/ ;set up rambar to place ram at $80000000
2) Processor has a software watchdog that needs to be disabled WRITE_WORD=0000/40140000/ ;kill extra sw watchdog
3) External bus interface is not properly configured after bootup WRITE_WORD=0000/40000080/ ;CSAR0 - CS0 at address 0 WRITE_LONG=00000101/40000084/ ;CSMR0 - Enable CS0 WRITE_WORD=3D80/4000008A/ ;CSCR0 16-bit data bus
Troubleshooting - Make sure you are using the correct algorithm. Please refer to this previous blog post for more information about algorithm selection. - Double check hardware connections between the processor and the external flash. - Check if the processor is actually able to access the external flash. The PROG software has a command called “Show Module” which will attempt to read the contents of the flash. If the data is displayed as XX, then the processor was unable to read the external flash. - If the hardware connections are good but the processor’s external bus configuration needs tweaking, a debugger will allow you to check the processor’s settings on bootup to make sure they match up with the external flash.
P&E has updated its Cyclone PRO Image Creation Utility to provide a way for users to set a custom trim frequency for HCS08, RS08, and CFV1 devices that have an internal reference clock. To use this feature, the user must first select a programming algorithm, because not all devices have the same maximum and minimum internal reference clock frequencies.
Once the programming algorithm has been selected, the utility will determine the allowed frequency range from which the user can choose. The user also has the option of enabling or disabling this feature. When it is enabled, the user can input a desired frequency. If the user does not enable this feature and input a frequency, or if this feature is disabled, the utility will simply select the default trim frequency as specified in the device reference manual.
Please note that this feature is only effective if the "PT ; Program Trim" command is included in the programming sequence. This custom trim feature in the updated Cyclone PRO Image Creation Utility is similar to the one available in CodeWarrior for Microcontrollers (RS08/HC(S)08/ColdFire V1).
To download the latest updates, please visit our Cyclone PRO product page.
P&E’s PROG programming software will sometimes prompt the user to enter a “Base Address”. In this article, we discuss what the base address is and why it exists.
On most 8-bit and 16-bit processors, the internal flash/eeprom is located at fixed address locations. If this is the case, the associated programming algorithm will NOT prompt the user for a base address, since the address is fixed and already known.
On 32-bit processors and any systems using external flash, the address of the flash may be configured to reside anywhere within the processor’s address space. The developer will decide on an appropriate memory map early in the design process.
For these situations where the flash can be relocated, the PROG software will always move the flash so that it begins at address 0. However, the developer may not have an object file that matches this new memory mapping. To account for this, the “Base Address” (specified by the user) is subtracted from all addresses in the object file prior to programming.
Below is an example of how the developer’s memory map may differ from the one in PROG. Although the external flash is located at different addresses, it refers to the same physical memory. Here, the user would specify a base address of FFC00000.
The base address should always be the starting address of flash in the developer’s memory map, and not the “first” address where data exists (although in most cases they are the same!)
Today's tip concerns P&E's Cyclone automated programmers. With the release of the Cyclone Automated Control Package,
users have been inquiring if there is a way to automate the creation of stand-alone
images. Fortunately, with the standard Cyclone
PRO/MAX installations, users already have command-line executables that
can accomplish this task.
For each architecture there is a corresponding CSAPXXXX.EXE application that can be used to create a stand-alone image file. For example, to create an image for the Coldfire V2/V3/V4 devices, the user would use CSAPBDMCFZ.EXE. For this blog, we will demonstrate how to create a stand-alone image for a 9S08QE128 device by using CSAPHCS08Z.EXE.
Begin by creating a stand-alone configuration file. You can create a configuration file by configuring the programming sequence in the Cyclone Image Creation Utility and then saving it thorugh File ->Save Cyclone Configuration. You can also create a configuration file by using a text editor, typing in the commands, and saving it as a .CFG file. A typical configuration file might use the following sequence:
CM C:pemicrocyclone_proAlgorithmsHCS089S08QE128.S8P SS C: esthcs089S08QE128.S19 EM ;Erase Module BM ;Blank Check Module PT ;Program Trim PM ;Program Module VM ;Verify Module VC ;Verify Checksum
In this example, we will save the .CFG file as "9S08QE128.CFG" in c:. With the configuration file created, we can now create a stand-alone image or .SAP file by using the command prompt. In the command prompt, we can invoke the configuration script file as follows:
The first parameter, "c:9S08QE128.cfg", specifies the location of the input configuration file.
The second parameter, imagefile "c:9s08qe128.sap", specifies the name and output location of the .SAP file.
The last parameter, imagecontent "9S08QE128_1_26_2009", specifies the image description.
You can use the '?' character option to cause the utility to wait and
display the result of the configuration in the CSAP window. You can also use the '!' character option to cause the utility to wat and display the result only if the file
failed to generate.
After invoking the configuration script in the command prompt, the file 9S08qe128.sap is generated in the C: directory. The 9s08qe128.sap file can now be loaded into the Cyclone PRO/MAX by using the Cyclone Automated Control Package or the Cyclone Manage Images Utility.
P&E's Cyclone PRO makes it very simple to program both the Flash
and EEPROM on your HC(S)12(X) device. There is a
unique algorithm for each device and the type of memory, so the first
step is to determine the correct algorithm for your setup. A list of
all of our algorithms is located here. If you need help indentifying the correct algorithm, please refer to our previous post, Choosing The Right Programming Algorithm.
The following is a demonstration of how to program the 9S12DP256B microcontroller with P&E's Cyclone PRO, first in Interactive and then in Stand-Alone mode.
The 9S12DP256B has 4KB of EEPROM and 256KB (4 blocks of 64KB) Flash, so the algorithm files that you are need are:
You can place your code for EEPROM and Flash in seperate S-Record files or combine it into one. The P&E programming software will ignore any addresses in the S-Record that are out of memory range. Note that Freescale's Codewarrior Develoopment Kit automatically
outputs an S-Record file and PHY file that contain both the Flash and
EEPROM code. You can load the PHY file directly with either algorithm
When using the Cyclone PRO in Interactive Mode, open up the CyclonePro_PROG12Z Flash programming software and connect to the target board.
1. Load Freescale_9S12DP256B_1x16x2k_4k_EEPROM.12P with the "CM" command. 2. Specify S-record that you want to program with the "SS" command. 3. Erase the EEPROM with the "EM" command.4. Program the EEPROM with the "PM" command5. Verify the EEPROM with the "VM" command 6. Load Freescale_9S12DP256B_1x16x128k_256k_Linear_16k_page.12P with the "CM" command 7. Erase the Flash with the "EM" command.8. Program the Flash with the "PM" command9. Verify the Flash with the "VM" command
If you're using the Cyclone in Stand-Alone mode you'll need to configure the following programming sequence in the Cyclone PRO Image Creation Utility. If you don't have this utility, you can download the software here.
CM Freescale_9S12DP256B_1x16x2k_4k_EEPROM.12P SS DP256.PHY EMPMVMCM Freescale_9S12DP256B_1x16x128k_256k_Linear_16k_page.12PEMPMVM
P&E's ICD In-circuit Debugger and PROG Flash Programmer software, included with the Starter Editions, natively supports several object file formats, including s-record and ELF. Soon, P&E software will natively support Intel Hexadecimal files.
After installing one of the Starter Editions, run OBJCOPY from the Windows command-line. The program is located in the gnuin subdirectory within the installation directory. View the help screen for OBJCOPY from the command-line by typing "powerpc-eabispe-objcopy" or "m68k-elf-objcopy". You will see a list of all program options. To determine which formats are available with OBJCOPY, take note of the final lines of the help screen. You will use these format names, BFD names, when running OBJCOPY.
To convert a file, use the "-O" option followed by the name of the desired output format. The input format may be specified with the "-I" option, though this is often unnecessary. For example, to convert the object data in a COFF file "file1.coff" to an s-record file "file1.srec":
If you are looking for greater control of file conversion, look at the options on the OBJCOPY help screen. For example, with powerpc-eabispe-objcopy you may specify s-record length, force S3 records, and manipulate the linker sections in object files.
When using P&E's PROG family of programming software, it's necessary to specify the correct programming algorithm to match your hardware setup. Because P&E
provides thousands of different programming algorithms this can seem like a duanting task. In this article we discuss how to quickly determine the programming algorithm that correctly matches a specific hardware setup.
1) Obtain the latest Programming Algorithms P&E's Programming Algorithms are being constantly updated to support new devices. For convenience, all of our algorithms are located here. These algorithms are grouped according to the processor family being used.
2) Internal or External Flash/EEPROM? Internal Flash/EEPROM is memory that resides inside the processor itself. Although most modern processors contain at least some internal Flash/EEPROM, there are some specific devices (Freescale MCF5474) that do not contain any nonvolatile storage. External Flash is a separate integrated circuit component that is externally connected to the processor. In general, external Flash is used for higher end 32-bit applications that require increased memory capacity.
3a) Internal Flash/EEPROM Algorithm Selection Once you have identified the processor that you are working with, it is generally straightforward to identify the correct programming algorithm. All of P&E's internal Flash/EEPROM algorithms contain the processor part number in the filename. In certain cases, there are separate algorithms for programming the Flash and the EEPROM. This information is also present in the algorithm filename itself. All the algorithms for the processors in the same architecture end in the same file extension.
P&E's external Flash Algorithms use the following naming convention: Manufacturer_PartNumber_NumDevices x DataBusWidth x NumRows.FileExtension
Manufacturer = Manufacturer of the external Flash device PartNumber = Manufacturer Part Number NumDevices = Number of these external Flash devices used in parallel. Devices are typically used in parallel to support a wider data bus. As an example, imagine that an external Flash device only supports a 16-bit data bus. By using two of these devices in parallel, a 32-bit data bus can be supported. DataBusWidth = The data bus width of EACH external Flash device. Certain devices support multiple data bus widths. NumRows = The number of rows in each Flash device. Each row contains DataBusWidth bits. NumRows multiplied by DataBusWidth results in the total size of the Flash memory. FileExtension = The file extension is unique for each processor family.
ST_29W128FH_1x8x16meg.CFP - A single STMicroelectronics 29W128FH device, configured for 8-bit data bus. Total size = 8 bits (1 byte) x 16Meg = 16 MB ST_29W128FH_1x16x8meg.CFP - A single STMicroelectronics 29W128FH device, configured for 16-bit data bus. Total size = 16 bits (2 bytes) x 8Meg = 16 MB ST_29W128FH_2x8x16meg.CFP - Two STMicroelectronics 29W128FH devices, each configured for 8-bit data bus. The result is a 16-bit wide data bus. Total size = 2 x 8 bits (1 byte) x 16Meg = 32 MB
4) Device not supported?
This page can be used to request a specific Flash Programming algorithm if you do not find what you are looking for. Use this form if your device is not supported or if the existing algorithms do not match your setup correctly (e.g., if you are not using the default chip select). This service is provided by P&E free of charge.
Did you know that the Freescale Codewarrior IDE includes an
option that allows you to program flash with more flexibility? This option is
called “Expert Mode."
Expert Mode provides a set of general interface
functions which are used to control the erasing, verifying, programming and
viewing of modules to be programmed and provides the flexibility of choosing
your own flash programming algorithm and program/erase ranges in your module
within the IDE.
To access this feature, follow these steps:
Start the Freescale CodeWarrior IDE
Create your project or use an existing one.
the connection type is set to “P&E Multilink/Cyclone Pro” and your target
Start the Debug session and interface with the
Inside the real-time debugger, navigate to
“Start Expert Mode Programmer…” and select this option.
This will allow you to access features that are normally available to you
in P&E's PROG flash programming software. This option is available in CodeWarrior 6.2 for the HCS08
and RS08 architecture and allows the Cyclone PRO to be used for interactive programming.
To find full documentation of our software for your device,
P&E’s product line of Cyclone stand-alone
provides a fast, robust, and automated solution for production-scale
programming of microprocessors. However, production facilities may
even higher level of automation than the single-button touch capability
offered by the Cyclone. P&E offers several means of automating
control, including a command-line executable, UDP/Serial
communications, or the .DLL included in P&E's new Cyclone Automated
Control Software Package. In this article, we discuss automated control
using the automated control package and the unprecedented level of
power and flexibility that
1.) Introduction – Controlling a Cyclone through the PC
P&E’s new Cyclone Automated Control Package provides
the developer with a dynamic link library (DLL) and supporting documentation to
allow custom software applications to directly control the Cyclone.
By storing the binary data information, algorithm
information, and settings directly into the FLASH memory of the Cyclone,
programming operations can be initiated by the simple push of a button.
However, the DLL enables us to use the PC to issue a command to the Cyclone to
start the same programming sequence!
The use of a PC to control the Cyclone enhances the
functionality of the stand-alone programming operations, but also introduces
new capabilities that were not available previously. In the following sections,
we explore the features of the Cyclone Automated Control Package and present
practical examples of how to use it in your own production line.
2.) Setup – Image Creation
The first step is always to create the actual stand-alone
images that will be stored onto the Cyclone. These images contain the algorithm
needed to program FLASH / EEPROM, the actual binary data to be programmed, the
sequence of programming operations, and many user-specified Cyclone settings.
P&E’s “Cyclone Image Creation Utility” allows the user to properly
configure the stand-alone images.
Above is a screenshot of the dialog in the Cyclone Image
Creation Utility which allows the user to configure the stand-alone image. The
field on the right shows the programming steps and also the order in which
these steps execute.
1.)First, we select the appropriate algorithm for our
processor. In this example, we are using the Freescale
2.)Next, we specify the target object file that represents
the binary data to be programmed into the processor’s FLASH memory. Here, we are
using a Motorola S-record file.
3.)Once the algorithm and the target object file are
specified, we are ready to begin programming. Typically, the procedure is to
erase the device to make sure it’s blank, program the target, and verify that
the contents were written correctly.
In addition to the programming sequence, there are also
settings for the Cyclone that we can configure. In the above screenshot, we are
using the Cyclone PRO’s power relays to provide the appropriate voltage to power
up our processor. This way, we do not need a separate power supply for our
target board, simplifying our production line.
Finally, we specify the Image Description so that we can
easily identify the image later on. By using the “Store Image to Disk” option,
we are able to save this image and its configuration as a .SAP file for future
3.) Using the DLL – Simple Example
The above code example shows the most basic operation that
is supported by the Cyclone Automated Control Package. Below are the steps we have
Step 1: Contact the desired Cyclone by specifying its
IP address. The handle of the Cyclone is returned, and is used to identify the
Cyclone in all subsequent function calls.
Step 2: Send a command to the Cyclone to begin the
programming operations specified in image #1. These operations were specified
during the image creation process.
Step 3: Wait for the Cyclone to complete the
programming operations before proceeding.
Step 4: Check to see if any errors occurred during
programming and provide a message to the user.
Step 5: Terminate the current session with the
4.) Using the DLL – More Advanced Operations
Programming a serial number
Note: The following are placeholder functions used to
simplify the example, and are not provided by the automated control package:
The above example code is an event handler written for a
visual MFC application, which is executed each time a button is pressed by the
user. Here, we again instruct the Cyclone to perform the stand-alone
programming operations of the image stored on the Cyclone. Afterwards, we
program a dynamic 2-byte serial number into address 0x100 of the target
processor. The serial number is then incremented and written back to a file for
Although there are many different ways to program a serial
number without needing to use the automated control package at all, this code example can easily be
modified to program dynamic data that is not sequential. For example, if we
wish to program the current date or a lot number, using the automated control package and writing
your own custom application is by far the easiest and most automated way to
accomplish this task.
Automatically update image stored on the Cyclone
This is a very simple example of how to ensure that the
image stored on a Cyclone is always up to date. A comparison is performed
between the image which currently resides on the Cyclone and an image file at a
specified location on the host PC. If there is a mismatch, then we update the
image. Afterwards, we proceed with the normal programming operations as seen in
the previous examples.
5.) Can I Control Multiple Cyclones?
Up until now, we have discussed some uses of the
Cyclone Automated Control Package with a single Cyclone unit. Since the host PC only
sends minimal control information to control each Cyclone, a single PC is
actually capable of controlling many Cyclone units simultaneously.
Here, we begin programming operations on 3 separate Cyclone
units and wait for their completion before proceeding. In essence, we are
programming 3 separate devices in parallel. This can be easily extended to 10,
100, or even 1000 Cyclone units controlled in parallel from a single host PC!
6.) More Examples
Here are a few more real world examples:
·Quality Control : automatically
record statistics on the number of devices that fail during programming.
·You’re a developer and just completed the
firmware development for a brand new product. Now you need to get your
production facility up to speed, but they are halfway across the country.
Streamline this process by writing a simple application that will add a new
image to the Cyclone. Send this along with the new stand-alone image SAP file
and you’re done.
·You use multiple Cyclone units for programming
your devices in parallel. Each Cyclone has 4 different images, one for each of
your 4 different products. Write an application that allows the user to
automatically select the correct image for the current production run.
Whether you are performing small production runs in-house or
programming a large number of chips in a high-volume facility, P&E’s
Cyclone product family provides a powerful, yet affordable, solution. With the
advanced parallel programming, image management, and error tracking features
provided by P&E’s new Cyclone Automated Control Package, you now have the power to
completely automate your production programming process like never before.
Did you ever wonder how to power cycle your device to force it into
Background Debug Mode? Are you trying to eliminate an external
power supply from your manufacturing setup? You can accomplish either task by using
a Cyclone PRO. Using the Cyclone PRO's internal power generation mechanism, you can control power for any HC08/HCS08/RS08/HC(S)12 device.
In fact, controlling the power through a Cyclone PRO is crucial for
HCS08/RS08 device applications which may not have a dedicated RESET
pin. This is because power cycling the device is necessary in order to fully automate the
FLASH programming procedure.
To configure a Cyclone PRO to provide power to pin 6 of the BDM
header, set power jumpers 2, 3 and 4 on the side of the Cyclone unit. To
provide power to pin 15 of the 16-pin MON08 header,
set power jumpers 1, 2 and 3. Once the power jumpers are set,
select "Provide Power to Target" from the Connection Assistant and/or
Cyclone Image Creation Utility and the Cyclone PRO will take care of
the rest. You can choose between 5V, 3V and 2V levels.
Cyclone PRO is also able to toggle power for most high-power/high-voltage devices. The internal electromechanical relays can handle power supplies with a maximum switched current of 1A and a maximum switched
voltage of up to 30VDC. In order to automate power cycling with an
external power supply, insert it into the Cyclone's "Target Power In" jack. Use the power cord that's included in the Cyclone PRO kit to
connect the output of the Cyclone's "Target Power Out" jack to the power input of your
board. Then be sure to set power jumper 5 on the side of the Cyclone unit, leaving jumpers 1, 2, 3 and 4
One of the most valuable features of P&E's Cyclone PRO and Cyclone MAX is the stand-alone mode, which allows users to program their boards without the need for a host PC. The purpose of this post is to visually show our newest users how to quickly configure their unit for production line programming.
Make sure you are using the latest Cyclone PRO/MAX installation software. If you are
using an older SAP Configuration utility, you should uninstall it before installing the latest version. Reboot your PC after the install is completed.
Open the Cyclone Image Creation Utility. Create your programming script by
double clicking on the commands under the "Programming Sequence" panel
or use the Launch Script Wizard. After completing the stand-alone
configuration, click 'Store Image to Disk' to save the current
configuration onto your hard drive as a .SAP file. Save each
programming script you create as a different .SAP file.
Open the Cyclone Manage Images Utility. Choose the appropriate port and
click open. Press Add to bring up the Add Image to Internal Memory
dialog box. Select the .SAP file that was previously saved. Repeat this
until all your SAP files have been added. Then press Commit Changes.
Click "Yes" on the confirmation dialog box. The images will then be loaded
onto your Cyclone PRO/MAX.
4. The stored images will appear on the "Images currently on the Cyclone" panel.
View FAQ 110 for download links to the Cyclone PRO and Cyclone MAX software.
In a previous post, we showed how to use PKGPPCNEXUS and PKGCFZ_PRO to display the contents of an ELF/DWARF file using Readelf. In this post, we look at the Readelf output and explain its description of your object code.
We will use this example Readelf output to illustrate the kinds of information that Readelf provides.
The first item of interest is labeled "Entry point address". This is the address of the first instruction executed after reset. Your compiler or linker determines this value. The P&E debugger optionally uses the entry point address to execute your target application.
The "Section Headers" portion lists all of your linker sections that made it to your ELF/DWARF file. The ".debug_info" section is where ICD looks for the debugging information entries. Note that not all of these sections contribute to the application memory map.
The portions titled "Program Headers" and "Section to Segment mapping" describe the application memory map. ICD and PROG use the program headers to determine where to place object code on your target. Check that a linker section is included in the final memory map by examining the section to segment mapping. Note that the first entry in the program headers corresponds to the first entry in the section to segment mapping.
From the program headers, you can gather the following information about the memory map: Type - Only LOAD types contribute to the final memory image VirtAddr - load time location of code MemSiz - number of bytes that the code segment occupies in the final memory image
P&E's PROG and ICD software support an uncommon feature of the GNU compiler. GCC uses both the program header VirtAddr and PhysAddr fields, the former for run time address and the latter for load time address. For more information on this useful feature, please refer to this document.
When using either a Cyclone PRO or a Cyclone MAX, customers often ask whether programming a target through Ethernet is faster than USB or vice versa. While it's certainly true that the transfer time of data from the PC to the Cyclone occurs faster over an Ethernet link, the actual programming time is bottlenecked by the BDM Shift Frequency.
BDM Shift Frequency refers to the rate at which signals are handshaked (shifted) from one of the interface ports of a Cyclone unit to the Background Debug port of the target unit. This handshake can occur synchronously or asynchronously, the former requiring the presence of a clock source (note that some ColdFire devices such as the MCF5272 require a synchronous interface), and may also require a power cycle sequence as part of entry into background mode, which is performed automatically by the Cyclone PRO.
BDM Shift Frequency directly reflects the operating clock frequency of the device. For example, a ColdFire processor operating at 200 MHz will support a much faster BDM Shift Frequency than the same processor would if operated at a slower speed of 50 MHz. Because processors can be configured to operate at different frequencies given an identical clock source, we take advantage of this and programmatically put the processor into a faster gear when possible by configuring the appropriate PLL entries from our programming algorithm.
How fast can the BDM Shift Frequency be? The answer isn't uniform across all processors and can be found in each processor’s specific user’s manual. However, the rule of thumb is to use a value which is at most one-fifth of the bus clock frequency of the device, while keeping in mind all pertinent signal integrity issues and using proper cable length for connection to devices which operate faster than 100 MHz (see earlier post regarding cable length).
In short, whether using Ethernet or USB, or even in Stand-alone mode, all programming times are ultimately bounded by the BDM Shift Frequency that you select. It often pays to experiment to identify the fastest BDM Shift frequency, given the guidelines above, and to select the rate for the fastest programming times.
Did you know you can safeguard data while erasing your Flash/EEPROM module during programming? P&E has added a “preserve range” function that can be used in a programming algorithm to preserve memory ranges. The function looks at the range to be preserved, saves it, and restores it after the Flash/EEPROM has been erased. The user can easily preserve code segments stored in flash with a couple of modifications to the header of the programming algorithm.
A flash programming algorithm is a text file which describes how a particular flash block is to be programmed. The algorithm contains a configuration section as well as some s-record data which implements the programming process. User's commonly will modify the configuration section to change the behavior of the programming algorithm, such as to add ranges of data to preserve.
Flash algorithms describe flash blocks as having either a fixed address (common for internal flash on a microcontroller) or a variable address (common for flash chips external to a microprocessor). Algorithms which do not have a fixed address for the flash will prompt the user for the base address of the flash at the time of programming. In either case, the algorithm can be used to specify ranges of flash to preserve relative to the start of the flash block.
For an algorithm with a fixed address for the flash block, the following line will indicate the flash block location:
NO_BASE_ADDRESS=NNNNNNNN/ ; NNNNNNNN is a Hexadecimal value indicating the start of flash
Do not modify the NO_BASE_ADDRESS line! You are simply going to add some lines after it which indicate that you wish to preserve certain ranges relative to the base address. The configuration line(s) you should add directly after the NO_BASE_ADDRESS line should have the following format (very strictly formatted - no spaces allowed and include all forward slashes):
PRESERVE_RANGE=SSSSSSSS/EEEEEEEE/ ; SSSSSSSS is the starting offset, EEEEEEEE is ending offset
Adding this line would preserve the following memory range : NNNNNNNN+SSSSSSSS to NNNNNNNN+EEEEEEEE.
If there was an algorithm which was designed to program a flash block with address range $4000-$FFFF, you would see the following configuration in the flash algorithm:
NO_BASE_ADDRESS=00004000/ ;Fixed at $4000 ADDR_RANGE=00000000/0000BFFF/00/FFFFFFC0/FFFFFE00/ ; $4000-$FFFF
Do not modify these lines! If you wanted to preserve a certain memory range, you would specify it after the line with the NO_BASE_ADDRESS command (which sets the base address) and before the lines with ADDR_RANGE. If you wanted to preserve the memory from address $F000-$F001, you would add the bolded line as follows:
Note that the preserve_range command requires the offset from the base address of your memory. If you add $4000 to $B000 and $B001, you have $F000 and $F001.
In addition, this functionality does not limit the user to preserving only 1 range or one address. The function can be called several times in the algorithm if several ranges and/or addresses need to be preserved, or if the Flash/EEPROM is segmented into several fields or extended into pages.
For the flash block above (from $4000 to $FFFF), if the user wished to preserve addresses $5001, $5006 and ranges $CCAA-$CCBB and $D123-$DFFF, the following segment would be added to the algorithm:
It is also possible to preserve several different segments across different pages of Flash/EEPROM. The user should know how to access each page of memory logically in the software. Let's look at the HCS08 AC128. The paged Flash memory can be accessed with the following ranges. This will typcially be described in the configuration section of the programming algorithm.
$08000-$0BFFF --> Page 0 $18000-$1BFFF --> Page 1 $28000-$2BFFF --> Page 2 $38000-$3BFFF --> Page 3 etc. If the user wanted to preserve memory on page 0 from $08000-$08005 and on page 3 from $38000-$38005, he would add the following commands :
Note again that the offset $20F0 is added to the parameters of the command to calculate the correct paged memory ranges to preserve. Add $20F0 to $5F10 to get $08000 and add $20F0 to $35F10 to get $38000.
The PROG software will report a checksum error and warn that the algorithm has been modified. This error can be ignored. If you wish to remove the warning, please use our command-line ADDCRC utility to update the checksum.
The Blank Check command will now fail because of the preserved data. Also note that the Verify Module command will ignore the addresses that are preserved when comparing memory against an S-record.
Any information which follows a semicolon (;) on a configuration line is a comment. P&E can provide more a detailed specification of flash algorithm construction upon request.
The HC(S)12(X) microcontroller family uses a paged flash architecture to expand its addressable memory beyond the standard 64KB (or $0000 to $FFFF). Microcontrollers with this feature treat a 16KB block of memory from $8000 to $BFFF as a memory window. This window allows multiple 16KB blocks to be switched into and out of program memory. An 8-bit program page register (PPAGE) tells the microcontroller which block to read.
The entire paged memory can be addressed in two different ways: logical or physical. Logical addresses are treated as segments of 16KB separated by 48KB. These segments (or pages) of memory occupy $8000 to $BFFF. In addition to the page window, there are two fixed 16KB blocks from $4000 to $7FFF and $C000 to $FFFF. These fixed locations are addressable in either range. For example, the last page of the MC9S12DP512 is $3F8000 to $3FBFFF or $C000 to $FFFF. Physical addresses treat the whole flash as one linear space in a 24-bit memory map. For example, the physical address space of the MC9S12DP512 is $080000 to $0FFFFF.
To program the flash with P&E's software, you need an S-record file that has physical addresses by definition. If you have a logical file, you can use the Log2Phy tool to convert it to an S-record. Select the microcontroller from the drop down box in Log2Phy. Then load the s-record and type in the name of the output file. Press the Convert button and the results of the conversion will appear in the box. The S-record file is saved to a file with the extension “.phy”. If there are unconverted logical addresses, they are saved to a file with the extension “.s19.extra”.
The Log2Phy tool now supports all S12, S12X, S12XE, and S12P devices.
This is a screen capture of the Log2Phy tool showing the conversion of a logical file for the MC9S12DP512 to an S-record:
This is the assembly source with sample code:
; Device = MC9S12DP512
org $8000 ;page 20 is the first page dw $8000 ;physical address $80000 org $BFFE dw $BFFE ;physical address $83FFE
P&E has added a new Chip Select Diagnostic mode to its interactive
flash programmers to allow the user to diagnose memory map configuration
P&E’s flash programmers support an extensive array of
external flash devices connected to the processor. P&E’s algorithms are designed to work by default when
the flash device is connected to the boot chip select and no modification is
needed to the reset configuration of the output enable and write enable lines. However, there are numerous ways in which the flash can be
connected that may require changes to the default reset configuration
of the processor’s chip select, write enable, and output enable operation.
When another configuration is used, the algorithm may
require some modification to work. This
often involves writing to the chip select registers to change which chip select
is used, to make certain chip selects read only or write only, or to change the
base address of the chip select. P&E’s algorithms expect the flash to be located at a
specific location in the memory map. This location is listed in the algorithm
itself as a comment. An example can be seen here:
This line indicates that the flash must be configured to be
in the memory map at address 0, and that the full range $00000000-$00800000
must be configured to address the flash. This is separate from the “Base
Address” capability in the programmer user interface which makes the flash
appear to be anywhere the user selects it (internally it physically resides at
a specific location).
On many devices the boot chip select is enabled everywhere.
If a configuration change is needed, there are many commands which allow the
registers on the device to be written during startup. The WRITE_LONG,
WRITE_WORD, and WRITE_BYTE commands are examples of commands which can be used
to write to memory mapped registers. There are also commands on some
architectures to allow the configuration of where the registers are located,
such as the CONTROL command on the ColdFire architecture. Here is an example of
initializing the CS1 chip select on a 5272 device instead of the default CS0
chip select (the boot chip select).
CONTROL=20000001/0C0F/ ;set mbar on with address $20000000
WRITE_LONG=00000078/2000004C/ ;proc=5272 cs=CS1 on
The question often comes up : How do I know my chip select
configuration is correct?
P&E has added a diagnostic tool to it’s interactive
flash programmers which allow the user to test the chip select configuration to
make sure the chip select, write enable, and output enable signals have been
properly configured. The utility may be chosen from the “ChipSelectsDiagnostic”
selection on the main menu bar. A portion of the utility is shown here:
The user will need a scope or a logic probe to see if the
signals maintain the proper state during the test read and test write functions.
Setting the chip select registers properly solves the majority of support
questions P&E receives regarding external flash algorithms.
Certain test procedures and production environments
require the use of a cable longer than the typical 9-inch flat ribbon cable
typically included with P&E hardware interfaces. Extending the cable length
requires special considerations for signal integrity, crosstalk, and
electromagnetic interference. Simply using a longer cable without understanding
these topics will usually produce a setup that does not work reliably, if at
all. Extending the ribbon cable should be the option only if you determine that you cannot make longer the length of the USB, Ethernet, or Serial cable that connects the P&E hardware interface to your PC. The cables for the communication ports already have some shielding.
is necessary to use a longer ribbon cable, P&E recommends using a shielded jacketed cable . This cable configuration is excellent at
reducing crosstalk as well as minimizing electromagnetic interference from
other devices. Further improvement can be obtained if the wires are also arranged
in twisted pairs.
Shielded USB cables are inexpensive and easy to rework. The
four wires provided can be used to create a cable for the standard 6-pin BDM
header used by many Freescale microprocessors (such as the HCS08, RS08, CFV1, and HCS12). But this option won't work for other devices that require more debug pins.
In general, these guidelines should be followed for all cables between the target microprocessor and the P&E hardware interface:
shortest cable possible
shielded cable configurations to reduce parasitic effects
communication frequency. For the ColdFire or Qorivva architectures, the communication frequency is controlled by the BDM Debug Shift Frequency setting. For other architectures, the communication speed is only
dependent on the processor's bus
frequency. Reducing the bus frequency (ie. disabling the PLL) should
The debug signals for some ColdFire devices such as the MCF5272 and MCF5206 have to be synchronized before reaching the microprocessor. This additional requirement must be kept in mind.
For time-sensitive HCS08/RS08 applications the developer often needs to trim the internal reference clock in order to generate a desired bus frequency. P&E's HCS08 and RS08 Flash Programmers provide a command called “Program Trim” that allows developers to program a pre-calculated value to the non-volatile flash locations that are reserved for storing ICSTRM and ICSSC registers. These can then be loaded at run-time.
Here’s a demonstration of how the “Program Trim” command can be used to generate a bus frequency of 8 MHz on a 9S08QE128 microcontroller. For the 9S08QE128, the “Program Trim” command will generate a value that will trim the Internal Reference Clock to 31.25 KHz with an accuracy of up to +/- 0.2%. The command will then program the generated value to 0xFFAE and 0xFFAF. We will be working with an assembly file that configures the Internal Clock Source module and toggle Port A every 20 CPU cycles.
Configuration source file:
ROMSTART equ $2080
SOPT1 equ $1802
ICSC2 equ $0039
ICSTRM equ $003A
ICSSC equ $003B
PTAD equ $0000
PTADD equ $0001
sta SOPT1 ; Disable watchdog
sta ICSTRM ; Load TRIM bits from Flash and store it into ICSTRM
ora $FFAE ; Load FTRIM bit from flash and store it into ICSSC
and #$3F ; Set BDIV to Divide DCOOUT by 1
sta ICSC2 ; FLL factor= 512, therefore 31.25Khz*512/1=16 MHz=DCOOUT
; 16MHz/2=8MHz=Bus Frequency
mov #$ff,PTADD ; Set all PTAD pins as outputs
mov #$ff,PTAD ; Set all PTA outputs as high
mov #$00,PTAD ; 4 cycles
mov #$ff,PTAD ; 4 cycles
jmp loop ; 4 cycles
dw Main ;Reset Vector
After saving the above source file section as "9S08QE128_Example.asm" and assembling it, we can use PROGHCS08 to program the generated 9S08QE128_Example.s19 file into flash. The programming sequence outlined below will program our generated .S19 and the pre-calculated trim value.
CM ; Choose module 9S08QE128.S8P SS ; Specify our object file 9S08QE128_Example.S19 EM ; Erase module BM ; Blank check module PM ; Program module VM ; Verify module PT ; Program Trim Value
On a power-on reset, our 9S08QE128 target will disable the watchdog, load trim values from flash and store them into their corresponding ICS registers, set the bus frequency divider to 1, and toggle PTA pins every 20 cycles. With a bus frequency of 8MHz, if we were to put a scope on any of the PTA pins, we would expect to observe a signal with a 400 KHz frequency +/-0.2% accuracy.
P&E's Cyclone programmers are sophisticated and flexible tools designed for in-circuit flash programming. Field service updates, an important part of a field system, often occur in places where there is no access to a PC or power outlet. However, P&E's Cyclones are lightweight, compact programmers that have been designed to operate in stand-alone mode – i.e. they can be loaded with a programming image, detached from the PC, and then be controlled via the LCD menu and control buttons. This makes it simple to update the firmware of a field system, for example. In the field, the Cyclone unit may be powered by using a Cyclone_PowerPack, which is a lightweight and compact lithium ion battery. The combination of the Cyclone programmer and the battery pack creates a fully operational field programming setup that is lightweight, compact, and extremely portable.
All that is required for a field update is to connect the battery-powered, pre-programmed Cyclone to the target. Flash programming occurs directly from the Cyclone image to the target by a simple touch of the Start button. Once initiated, programming launches and the on-board LCD displays the current state of the programming process. The final result, which is displayed on the LCD screen and with highly visible LEDs, clearly indicates a successful programming result.
If you use the ELF/DWARF file format with P&E's Programming or Debugging software, download one of our free C development kits to view the information within the ELF/DWARF file. Use Readelf to examine your application memory map, check your linker script, determine application size, view detailed debugging information, and more.
We include the GNU Readelf utility with our C development kits, PKGPPCNEXUS for PowerPC 55xx and PKGCFZ_PRO for ColdFire. These packages give you a complete set of development tools including the P&E ICD debugger, PROG Flash programming software, register viewing software, WinIDE editor, target specific project templates, and a GNU compiler toolchain.
You can control Readelf and the entire compiler toolchain from WinIDE. During compilation, you can automatically process the compiler output file with Readelf and dump the information to a text file. Also, take advantage of Readelf with any target architecture - if you're not targeting ColdFire or PowerPC 55xx, you can install one of our free C development kits and use WinIDE as a stand-alone ELF/DWARF viewer.
P&E has updated its ColdFire software products so that they no longer require use of the processor status (PST) pins on the debug connector. These pins are traditionally used to determine if the part is running in user mode or halted in debug mode. The default is still to use the PST pins for status, but this can be optionally disabled in the connection assistant. When disabled, the software will use the BDM communications pins to determine the processor status. This results in a slight slowdown in communication and download rates, but the advantage is that the target board no longer has to wire the PST signals to the debug connectors. This also alleviates some problems in the case where the customer application needs to make use of the alternate functions of the processor status pins instead of using them for debug.
, MA— P&E Microcomputer Systems continues its commitment to
programming automation and efficiency by announcing the release of an
Automated Control Software Development Kit (SDK) for the Cyclone family
SDK features a dynamic link library (DLL) and supporting documentation
which allow the user to create custom software applications that
directly control P&E’s Cyclone PRO and MAX units. It also enables
users to control multiple Cyclones with a single PC, modify stored
images, manage multiple images, and program non-sequential dynamic data
such as serial numbers.
Cyclone Automated Control SDK is available in Professional and
Enterprise versions to suit both small and large production scales. A
Basic version with limited features is available for download at no
More information is available on the P&E website on this link.
- P&E Microcomputer Systems announces that it has extended the support
of its PowerPC Nexus tools to include Freescale’s new MPC56XX devices.
This set of in-circuit debuggers, FLASH programmers, and hardware debug
interfaces now supports both MPC55xx and MPC56xx devices, offering a
comprehensive solution for Freescale’s advanced automotive microprocessors.
- P&E Microcomputer Systems announces the release of an upgraded
version of the Professional ColdFire Development Package for the Cyclone
MAX and ColdFire Multilink. The package is already a powerful
and inexpensive development suite for the Freescale ColdFire MCF52xx,
MCF53xx, MCF54xx microcontroller families. These tools have now been
extended to include support for the ColdFire V1. The professional
package supports the GCC toolchain compiler and GNU target template
projects, specifically for the ColdFire V1, and additional GNU template
projects for the ColdFire V2 (MCF52xx, MCF52xxx).
- P&E Microcomputer Systems now offers a rechargeable Power Pack
for use with the Cyclone PRO and Cyclone MAX stand-alone programmers.
When powered by a lithium ion long-runtime battery, a Cyclone unit is
the perfect solution for field firmware updates that require portable,
stand-alone programming. The Cyclone and PowerPack are lightweight,
compact, and extremely portable.
- P&E Microcomputer Systems’ Cyclone MAX is an extremely flexible
tool designed for in-circuit flash programming, debugging, and testing
of Freescale microcontrollers. The Cyclone MAX’s architecture
support has now been extended to include the PowerPC Nexus family (MPC55xx).
Architectures already supported include the ColdFire (MCF5xxx), PowerPC
(MPC5xx/8xx), and ARM (MAC7xxx).
- P&E Microcomputer Systems announces the release of the DEMOJM
development board, available through Freescale. The DEMOJM is a low-cost
development system that supports Freescale MC9S08JM60 and MCF51JM128
64LQFP microcontrollers. It consists of a DEMOJM Base Board, a DC9S08JM60
Daughter Card and a DC51JM128 Daughter Card. P&E’s Embedded Multilink
circuitry on the DEMOJM board allows the processor connected to the
DEMOJM to be powered, debugged, and programmed via USB from a PC.
- The ColdFire V1 professional development packages are complete, powerful,
and inexpensive development suites for Freescale ColdFire 51xx family
microcontrollers, including the JM and QE families. The package is now
available in either a C-level or ASM Development Suite. Packages include
P&E's in-circuit debugger, flash programmer, development environment,
assembler, register decoder. The C-level package also includes the GCC
C Compiler. A P&E debug interface is used to connect to a
standard debug connector on target and provides the ability to debug
in real time.
- P&E Microcomputer Systems announces the release of the DEMOQE128
development board, a low-cost development system designed for demonstrating,
evaluating, and debugging the Freescale MC9S08QE128 and MCF51QE128 microcontrollers.
P&E’s Multilink circuitry is embedded onto the DEMOQE128 board
so that it can be powered, programmed, and debugged via USB from the
PC. An optional BDM port is provided to allow use of an external BDM
interface such as P&E’s Cyclone PRO automated programmer or USB
Massachusetts - P&E has released a suite of development tools for
Freescale's 68RS08 family of microcontrollers. With this launch,
P&E now offers products to take an RS08 project from development to
production, including the DEVRS08KA2 low-cost development board and
P&E's popular Cyclone PRO.
addition to the DEVRS08KA2 development board, P&E has also launched
the ICDRS08 In-Circuit Debugger, PROG08 Flash/EEPROM Programmer,
WinIDERS08 Development Envirionment, and a package which combines the
USB-ML-12E USB Multilink BDM Interface with the RS08 debugger,
programmer, and IDE. The package also includes an RS08 simulator and
RS08 family of microcontrollers are reduced-core versions of the S08
architecture, designed with a focus on very small and highly portable
Boston, Massachusetts - P&E
Microcomputer Systems announces the release of the powerful but
cost-effective $99 ColdFire MCF5213 Development Kit. This kit includes
the DEV5213CF evaluation board, which features an embedded P&E USB
to BDM interface. The embedded interface provides for easy debug and
FLASH programming of the resident ColdFire MCF5213 processor. The
resident MCF5213 device is a 32-bit ColdFire processor which
incorporates 256KB of flash, 32KBytes of ram, ADC, QSPI, PWMs, timers,
a PLL, I2c, QSPI, and more. The processor runs at a system clock speed
of up to 80MHZ, with 76MIPS of performance.
64K Starter Edition of the P&E’s PKGCFZPRO software development
package is also incorporated into the MCF5213 kit. This software suite
provides user with the capability to compile, debug, and flash program
up to 64KB of user C code. This software suite includes the P&E
In-Circuit Debugger, Flash Programmer, and WinIDE integrated
environment, with a built-in GCC Compiler. The 64K Starter Edition also
includes a sample template project to give you a jump start on an
interrupt driven firmware design.
- P&E has released a complete, powerful, and inexpensive C-level
Windows-based development suite for Freescale PowerPC MPC55xx
processors. The package includes P&E's in-circuit debugger, flash
programmer, development environment, GCC C Compiler, assembler,
register decoder, and USB-ML-PPCNEXUS hardware debug interface. The
USB-ML-PPCNEXUS debug interface is a high speed USB 2.0 peripheral
which connects to a standard Freescale MPC55xx debug connector and
provides the ability to debug your target in real time.
P&E has also released a 64K-limited edition of the development suite which a available for download at no cost.
Massachusetts - P&E has released a complete, powerful, and
inexpensive C-level Windows-based development suite for Freescale
ColdFire MCF5xxx microcontrollers. The package includes P&E's
in-circuit debugger, flash programmer, development environment, GCC C
Compiler, assembler, register decoder, and USB-ML-CF hardware debug
interface. The USB-ML-CF debug interface is a high speed USB 2.0
peripheral which connects to a standard Freescale ColdFire debug
connector and provides the ability to debug your target in real time.
P&E has also released a 64K-limited edition of the development suite which is available for download at no cost.
Whether you are porting your existing C code to the GNU
compiler or creating an application from scratch, learning to use any new
compiler and development environment can be time consuming.For those who are new to GCC, setting up
compiler options, linker scripts, and target startup code takes even more
time.And, if you have never developed
a C application for an embedded system, then you might be working late a few
nights this week.PKGCFZ PRO reduces
your down time by simplifying all of these tasks.Follow the steps below to speed through the development process.
Boston, Massachusetts - P&E
Microcomputer Systems has expanded its offering of 68HC908 development
kits, with the addition of five new kits. Each new kit features a
development board with one of Freescale's 68HC908EY16, -GR8, -GZ60,
-SR12, or -QY4 processors, and a standard MON08 header. The kits also
include a USB-to-target MON08 interface (USB-ML-MON08) and P&E's
PKG08SZ software package.
also announced plans to offer development boards and kits featuring the
-AP64, -GT16, -KX8, -MR8, -QC16 in the near future.
Did you know that you can improve tracking of your products by placing serial numbers in flash during programming using P&E's FLASH/EEPROM programming products? There are commands in both the GUI (PROGxxZ) and command line (CPROGxxZ) versions of P&E's programming software for selecting a particular serial number file and
for programming the next serial number. The serial number is
incremented by one after it is programmed into your device. Complex
serial numbers with up to 16 bytes are supported. Each byte of a serial
number can be restricted to a range of values. This allows you to
create such things as printable, numeric, upper case alphabetic, lower
case alphabetic, and constant characters in your serial number.
P&E Microcomputer Systems, Inc. is pleased to annouce the release
of the Cyclone MAX automated programmer and debug interface. The
Cyclone MAX programs PowerPC (MPC5xx/8xx), ColdFire (MCF5xxx) and ARM
(MAC71xx) devices, and operates either as a stand-alone unit, or
connected to a PC. Like P&E's popular Cyclone PRO, the MAX allows
the user to communicate using either Serial, USB, or Ethernet ports.
P&E expects to add functionality to the Cyclone MAX, including the
possibilty of support for new architectures, expandable storage, and a
new visual interface.
Massachusetts— P&E Microcomputer Systems announces the launch of a
PRO development suite for ColdFire 5xxx devices. With the PRO suite,
P&E looks to expand on the success of its PKGCFZ, a popular,
cost-effective Windows-based development suite for the
Motorola/Freescale MCF5xxx microcontrollers. The PRO version now
represents a comprehensive solution for developing with either the C
language or assembly language. The GCC component of the PKGCFZ_PRO
Configure the compiler options within WinIDE
Run GCC directly from WinIDE and Windows - no complex UNIX shell is required
WinIDE builds your C application using a modifiable Windows batch file - no makefile is used.
Auto-create GCC initialization code and linker scripts for the ColdFire 527x/528x
Debug your C code using the ELF/DWARF(v. 2.0) file format
WinIDE highlights syntax errors in your C source code
PRO ColdFire packages are available in both parallel port and USB versions.
Microcomputer Systems, Inc. proudly annouces the release of a wide
range of development boards and kits for the M68HC908. P&E is now
offering affordably priced development boards for the M68HC908AB32,
-GP32, -GZ16, -JL8, -MR32, and -QY4. These boards are available
individually or as a set of all six. In addition, P&E is bundling
the boards with the MON08 Multilink, USB-ML-MON08, or Cyclone PRO
interfaces, providing the user with powerful yet inexpensive
development solutions right out of the box.
The development boards feature:
Resident MC68HC908 Processor (AB32, GP32, GZ16, JL8, MR32, and QY4)
MON08 Debug header to allow debug and programming from the Cyclone Pro, MON08 Multilink, or USB MON08 Multilink
access to all processor pins, including port pins needed for Monitor
Mode entry shortly after reset (wire wrap headers included)
P&E's asm/debug/programming software available at no-cost for download
Clock source may be from a P&E interface cable, on-board crystal (except QY4), or available to be driven by the user
Power may be provided by a P&E interface cable or by the user
Small size perfect for embedding into prototyping areas
Board dimensions: 2.3" x 2.125"
P&E also offers the boards as part of development kits, which include one of the following MON08 interfaces:
Massachusetts— P&E Microcomputer Systems continues to expand its
offering of USB Multilink BDM Interfaces by proudly announcing the
release of two new interfaces for the ColdFire and PowerPC families.
The USB-ML-CF is a USB-port-to-target BDM interface for the ColdFire
MCF52xx/53xx/54xx families of processors. P&E has also released the
USB-ML-PPCBDM, which is a USB-port-to-target BDM interface for the 5xx/8xx families of PowerPC devices. Both new USB Multilink BDM interfaces feature:
interface from PC to Multilink for fast programming and debugging, with
the ease and compatibility of the USB interface. Higher download rate
is over 3x faster than P&E's parallel port cable.
Wide target operating voltage of 1.80v-5.25v.
No separate power supply required - power is drawn from the USB interface (draws less than 1mA from the target)
As always, P&E is offering these powerful new tools at an affordable price. Please see the USB-ML-CF and USB-ML-PPCBDM product
pages on P&E's website for more detail.P&E Microcomputer
Systems, Inc., established in 1980 and located in Boston, MA, is an
industry trendsetter in hardware and software development tools for
Motorola / Freescale microcontrollers.