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ICDPPCNEXUS, P&E’s in-circuit debugger for the MPC55xx/MPC56xx processors, uses reset scripts to properly initialize the device when it comes out of reset. When these devices power on normally, the Boot Assist Module (BAM) automatically performs a default startup initialization.

However, if the processor is forced into debug mode, the BAM does not execute. Because of this, many of the processor’s resources, such as internal FLASH and internal SRAM, are not available until a proper reset initialization is manually executed. The ICDPPCNEXUS debugger uses reset script files to specify the exact initialization that should be performed immediately after the processor is reset and debug mode is entered.

ICDPPCNEXUS includes a set of these reset script files which initialize the processors with a standard configuration. These files have a .mac extension and can be viewed/edited with a standard ASCII editor such as Windows Notepad. Let’s take a look at some of these script files in more detail:

These commands set up an entry in the MMU to map the internal SRAM to begin at address 0x4000_0000. This is accomplished by writing to the MMU Assist Registers (MAS0 – MAS3) and then executing the “tlbwe” instruction. This type of setup is typically repeated for internal FLASH and peripheral modules.

Fatal errors can occur if an interrupt is triggered and the interrupt vector address points to an invalid memory region. The above commands configure vector addresses to point to the beginning of SRAM, which is a valid address.

This command initializes SRAM from 0x4000_0000 to 0x4000_FFFF by writing random data to this entire memory region.

The last example above is device specific. The SWT watchdog is disabled by writing a 0xFF00_000A to address 0xFFF3_8000. The core watchdog is also disabled by writing a 0 to SPR 340.





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