P&E has added a new Chip Select Diagnostic mode to its interactive flash programmers to allow the user to diagnose memory map configuration problems.

P&E’s flash programmers support an extensive array of external flash devices connected to the processor.  P&E’s algorithms are designed to work by default when the flash device is connected to the boot chip select and no modification is needed to the reset configuration of the output enable and write enable lines. However, there are numerous ways in which the flash can be connected that may require changes to the default reset configuration of the processor’s chip select, write enable, and output enable operation.

When another configuration is used, the algorithm may require some modification to work. Click through to see an example of a typical modification to a P&E algorithm, as well as how to run the new Chip Select Diagnostic tool.

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Certain test procedures and production environments require the use of a cable longer than the typical 9-inch flat ribbon cable typically included with P&E hardware interfaces. Extending the cable length requires special considerations for signal integrity, crosstalk, and electromagnetic interference. Simply using a longer cable without understanding these topics will usually produce a setup that does not work reliably, if at all.

If it is necessary to use a longer cable, P&E recommends using a shielded jacketed cable . This cable configuration is excellent at reducing crosstalk as well as minimizing electromagnetic interference from other devices. Further improvement can be obtained if the wires are also arranged in twisted pairs. Shielded USB cables are inexpensive and easy to rework. The four wires provided can be used to create a cable for the standard 6-pin BDM header used by many Freescale microprocessors.

In general, these guidelines should be followed for all cables between the target microprocessor and the P&E hardware interface:

1. Use the shortest cable possible

    

2. Use shielded cable configurations to reduce parasitic effects

    

3. Lower the communication frequency.

For certain architectures, this can be configured in software by the user. For other architectures, the communication speed is only dependent on the processor's bus frequency. Reducing the bus frequency (ie. disabling the PLL) should improve results.

For time-sensitive HCS08/RS08 applications the developer often needs to trim the internal reference clock in order to generate a desired bus frequency. P&E's HCS08 and RS08 Flash Programmers provide a command called “Program Trim” that allows developers to program a pre-calculated value to the non-volatile flash locations that are reserved for storing ICSTRM and ICSSC registers. These can then be loaded at run-time.

Click through to view a demonstration of how the “Program Trim” command can be used to generate a bus frequency of 8 MHz on a 9S08QE128 microcontroller...

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